# SEU-Hardened High-Speed SRAM Design with Self-Refresh and Adjacent-Bit Error Correction

## TL;DR

This paper introduces a high-speed SRAM design that improves resilience to radiation-induced errors using self-refresh and advanced error correction techniques.

## Contribution

A novel SRAM architecture combining self-refresh and SEABEC for enhanced SEU resilience with improved speed and error correction.

## Key findings

- The design achieves a 29.1% improvement in read/write speed and reduces SEU cross-section by an order of magnitude.
- Radiation experiments show nearly doubled SEU resilience compared to conventional SEC-DED designs.
- The design incurs a 14.2% overall chip area increase and a 95.2% dynamic power increase for the ECC module.

## Abstract

This paper proposes a high-speed static random access memory (SRAM) architecture that integrates a self-refresh mechanism with a novel single error and adjacent-bit errors correction (SEABEC) scheme to enhance resilience against single-event upsets (SEUs) in radiation-prone environments. By leveraging extended Hamming coding and dynamic circuits, the design achieves a 29.1% RW speed improvement, reduces SEU cross-section by one order of magnitude, and incurs a 29.8% area overhead and a 95.2% dynamic power increase of the ECC module, leading to an overall chip area increase of ~14.2% compared to static logic-based RH SEC-DED SRAM. Radiation experiments validate superior tolerance across a LET range of 1.63–21.8 MeV·cm2/mg, demonstrating nearly doubled SEU resilience compared to conventional SEC-DED-based designs. This work balances error correction capabilities with system efficiency, making it suitable for high-reliability applications in space electronics and advanced processors.