Source Field Plate Incorporated Monolithic Inverters Composed of GaN-Based CMOS-HEMTs with Double-2DEG Channels and Fin-Gated Multiple Nanochannels

TL;DR

Researchers developed monolithic inverters using GaN-based transistors with improved performance and breakdown voltage.

Contribution

A novel GaN-based CMOS-HEMT inverter with double-2DEG channels and fin-gated nanochannels is fabricated and characterized.

Findings

Monolithic inverters achieved noise margins of 2.03 V (low) and 2.10 V (high).

The inverter had rising and falling times of 4.9 μs and 3.2 μs, respectively.

Maximum breakdown voltage of 855 V was achieved with an optimized source field plate position.

Abstract

Monolithic inverters of CMOS-HEMTs consisting of D- and E-mode GaN-based devices were fabricated.

Characteristics of GaN-based MOS-HEMTs were influenced by the source field plate length.

Double-2DEG channels and fin-gated multiple nanochannels enhanced the device’s characteristics.

In this study, enhancement- and depletion-mode (E- and D-mode) GaN-based 120 nm-wide fin-gated multiple nanochannel metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) were manufactured on the epitaxial Al0.83In0.17N/GaN/Al0.18Ga0.82N/GaN two-dimensional electron gas (2DEG) channel layers grown on Si substrates using a metal-organic chemical vapor deposition system. The oxide layer grown directly by the photoelectrochemical oxidation method was used as the gate oxide layer in D-mode MOS-HEMTs. Furthermore, E-mode MOS-HEMTs used ferroelectric stacked LiNbO3/HfO2/Al2O3 layers as the gate oxide layers. The 120 nm-wide multiple nanochannels and various-length source field plates (SFPs) were fabricated and incorporated into monolithic complementary MOS-HEMTs (CMOS-HEMTs) consisting of D- and E-mode MOS-HEMTs. The resulting monolithic unskewed inverter was achieved by modulating the drain-source current of the D-mode MOS-HEMTs. The noise low margin of 2.03 V and noise high margin of 2.10 V of the unskewed monolithic inverter were obtained. From the dynamic experimental results, the rising time and falling time of the unskewed monolithic inverter were 4.9 μs and 3.2 μs, respectively. The breakdown voltage could be improved by incorporating an SFP. When the SFP edge was located at the center between the gate electrode and the drain electrode, the maximum breakdown voltage of 855 V was obtained.

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