# Enabling Radiation Hardness in Solid-State NAND Storage Utilizing a Laminated Ferroelectric Stack

## TL;DR

This paper introduces a new type of solid-state storage using ferroelectric transistors that can resist radiation damage, making it suitable for space and defense applications.

## Contribution

The novel use of laminated ferroelectric stacks in vertical NAND transistors significantly improves radiation resilience compared to traditional charge-trap NAND.

## Key findings

- Laminated FeFETs retain a full memory window and robust switching up to 10 Mrad (air) of total ionizing dose.
- Erased states degrade by only ∼2 V at 10 Mrad (air), with negligible drift after 1 Mrad (air).
- Laminated FeFETs show ∼30-fold lower threshold-voltage degradation per unit dose compared to charge-trap NAND.

## Abstract

NAND flash forms
the core of modern solid-state storage, which
is critical for data-intensive AI applications, yet charge-trap NAND
suffers rapid threshold-voltage (V
th)
degradation under ionizing radiation, causing reliability challenges
for space and defense applications. Here we show that ferroelectric
field-effect transistors (FeFETs) with laminated gate stacks offer
a promising route to achieving radiation resilience in vertical NAND
technology. We demonstrate that large-memory-window, vertical NAND-compatible
laminated poly-silicon-channel FeFETs with an 8 nm Hf0.5Zr0.5O2/3 nm Al2O3/8
nm Hf0.5Zr0.5O2 stack retain a full
memory window and robust switching up to 10 Mrad­(air) of the total
ionizing dose (TID). Programmed and erased states show negligible
TID-induced drift after 1 Mrad­(air), while only the erased state degrades
by ∼2 V at 10 Mrad­(air). Technology computer-aided design (TCAD)
modeling attributes these asymmetric shifts to state-dependent traps.
Compared to charge-trap NAND, laminated FeFETs exhibit ∼30-fold
lower V
th degradation per unit dose, positioning
them as superior radiation-resilient storage candidates.