# Comprehensive Comparison of Front- and Back-Illuminated Single-Photon Avalanche Diodes in 110 nm Standard CMOS Image Sensor Technology

## TL;DR

This paper compares front- and back-illuminated SPADs in a 110 nm CMOS process, showing that back-illuminated SPADs offer better near-infrared detection without compromising timing performance.

## Contribution

The study demonstrates that SPAD performance can be optimized through illumination and BEOL design without altering the junction structure.

## Key findings

- Back-illuminated SPADs show enhanced near-infrared photon detection probability (PDP) and broader spectral response.
- Timing jitter remains comparable between front- and back-illuminated SPADs at 72 ps FWHM.
- Backside illumination increases the diffusion tail, indicating a trade-off between near-infrared sensitivity and timing performance.

## Abstract

What are the main findings?
Front-illuminated (FI) and back-illuminated (BI) SPADs fabricated using the same 110 nm CMOS image sensor (CIS) process and identical front-end-of-line (FEOL) structures exhibit distinctly different spectral responses, governed solely by the illumination direction and back-end-of-line (BEOL) design.The BI SPAD provides enhanced near-infrared photon detection probability (PDP), while maintaining comparable dark count rate (DCR) and timing jitter performance to the FI SPAD.

Front-illuminated (FI) and back-illuminated (BI) SPADs fabricated using the same 110 nm CMOS image sensor (CIS) process and identical front-end-of-line (FEOL) structures exhibit distinctly different spectral responses, governed solely by the illumination direction and back-end-of-line (BEOL) design.

The BI SPAD provides enhanced near-infrared photon detection probability (PDP), while maintaining comparable dark count rate (DCR) and timing jitter performance to the FI SPAD.

What are the implications of the main findings?
We demonstrate that CMOS-based SPAD performance can be effectively optimized through illumination and BEOL engineering without modifying the junction structure or doping profiles.We provide practical design guidelines for selecting FI or BI SPAD architectures according to wavelength sensitivity and timing requirements in LiDAR and related applications.

We demonstrate that CMOS-based SPAD performance can be effectively optimized through illumination and BEOL engineering without modifying the junction structure or doping profiles.

We provide practical design guidelines for selecting FI or BI SPAD architectures according to wavelength sensitivity and timing requirements in LiDAR and related applications.

This paper presents a process-controlled study of illumination engineering in single-photon avalanche diodes (SPADs) fabricated in a 110 nm standard CMOS image sensor (CIS) technology. Front-illuminated (FI) and back-illuminated (BI) SPADs were implemented with identical front-end-of-line (FEOL) structures, including the junction and guard-ring configurations, enabling the isolation of the effects of illumination direction and back-end-of-line (BEOL) configuration without modifying the junction structure. Through TCAD simulations and comprehensive experimental characterizations, including current–voltage, light-emission, dark count rate (DCR), photon detection probability (PDP), and timing-jitter measurements, we systematically analyze the performance trade-offs introduced by the BI configuration. The BI SPAD exhibits enhanced near-infrared PDP and a broader spectral response due to its deeper absorption region and the incorporation of a metal reflector, while maintaining identical avalanche characteristics, as evidenced by an unchanged 72 ps full-width-at-half-maximum (FWHM) timing jitter. However, the backside illumination increases the diffusion tail, indicating a trade-off between near-infrared sensitivity and diffusion-related timing performance. These results provide design guidelines for optimizing SPAD performance through illumination-direction and BEOL engineering while preserving the FEOL design and demonstrate a useful approach for SPAD integration in standard CMOS technology.