# 3-Levels Vertically Stacked Si Nanosheet GAA pFETs with Low-Temperature Interface Treatment for Cryogenic Application

## TL;DR

This paper introduces a new type of transistor designed for cryogenic computing that reduces energy loss and improves performance at very low temperatures.

## Contribution

A 3-vertically stacked Si nanosheet GAA pFET with low-temperature O radical interface treatment for cryogenic applications is proposed.

## Key findings

- The device achieves an off-state current below 1 pA/μm at temperatures under 77 K.
- A saturated subthreshold swing of 15.4 mV/dec is achieved at 4.5 K.
- The interface treatment reduces DIBL by 25.4% and increases transconductance by 9% at 4.5 K.

## Abstract

Cryogenic CMOS technology provides a promising approach to surpass the Boltzmann limit and advance Moore’s Law, addressing the increasing demand for high-performance computing. However, at cryogenic temperatures, the subthreshold swing (SS) of the device saturates due to the band-tail effect. This study presents a 3-vertically stacked gate-all-around nanosheet (NS) transistor featuring room-temperature O radical interface passivation. This approach leverages the high reactivity of O radicals to minimize etch-induced damage, passivate interface defects, reduce thermal budget, and ensure uniformity in complex 3D structures. Structural characterization revealed a uniform 0.76-nm-thick interface layer, with a surface roughness of 0.103 nm and an interface trap density of 2.72 × 1011 cm−2·eV−1 at 300 K. Thereby, the band-tail-induced SS saturation at cryogenic temperatures is effectively mitigated. Experimental results confirm a lower characteristic temperature Tv for reaching the saturation plateau, and a saturated SS of 15.4 mV/dec at 4.5 K. Furthermore, reducing disorder-induced defects substantially suppresses the band tail state-assisted carrier emission, thereby minimizing subthreshold leakage. This enables the device to achieve an off-state current below 1 pA/μm at a temperature under 77 K, reaching 0.18 pA/μm at 4.5 K. Additionally, a reduction in 25.4% in drain-induced barrier lowering (DIBL), with a 9% boost in transconductance (Gm) peak is achieved at 4.5 K. The enhanced subthreshold switching, reduced leakage, and improved Gm in this interfacial-optimized NS FET strongly supports cryo-CMOS as a viable solution for energy-efficient computing.