Large-scale gate-all-around MoS2 transistor array through lossless monolithic 3D integration

TL;DR

A new 3D integration process improves the performance of MoS2 transistors by avoiding interface doping issues, making large-scale production feasible.

Contribution

A lossless monolithic 3D integration process is introduced to enable high-performance MoS2 gate-all-around transistors.

Findings

The process achieves an average on-state current density of 227 μA/μm with a peak of >335 μA/μm.

Gate-all-around transistors show a 46% reduction in resistance capacitance delay compared to planar structures.

The interface engineering strategy significantly reduces dielectric doping and improves transistor performance.

Abstract

Integrating 2D materials into 3D architectures can break through the physical limits of materials in advanced processes. However, challenges such as severe interfacial doping caused by dielectric deposition during vertical stacking processing have led to performance degradation in MoS2 3D gate-all-around (GAA) field-effect transistors (FETs), thereby severely hindering their large-scale integration. Here, we demonstrate a lossless monolithic 3D (M3D) integration process flow enabled by using an interface engineering strategy to achieve the highly uniform large-scale integration of multichannel MoS2 GAAFETs with ultrahigh current density. This strategy involves reducing interface states and dielectric doping by forming van der Waals contacts with MoS2 and creating hydrophilic surfaces for high-κ dielectric deposition via an Sb2O3 layer, thereby significantly improving the performance of the GAAFETs. The statistics of 112 GAA devices exhibit record-breaking performance, including an average on-state current density of 227 μA/μm with a peak value of >335 μA/μm, and an ideal minimum subthreshold swing approaching 60 mV/dec, all outperforming conventional back-gate transistors and other MoS2 3D FETs. Furthermore, Technology Computer Aided Design simulation confirms that gate-all-around transistors exhibit a 46% reduction in resistance capacitance delay compared with planar structures, further demonstrating enhanced gate control. This work establishes a manufacturing pathway for achieving the interface-doping-free deposition of gate dielectric layers, thereby addressing the performance-degradation issue caused by repeated processing steps in high-density M3D heterogeneous integration.

A lossless 3D integration process addresses interface-doping challenges, enabling high-performance MoS2 GAAFETs suitable for large-scale integration.

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