# Synergistic Effects of Additive Engineering in Enhancing the Performance of Sn–Pb Perovskite Thin‐Film Transistors and Derived Logic Circuits

## TL;DR

This paper shows how adding a specific chemical improves the performance and stability of perovskite transistors, making them suitable for use in electronic circuits.

## Contribution

A novel additive engineering strategy using BDTD is introduced to enhance Sn–Pb perovskite transistors and enable complementary logic circuits.

## Key findings

- BDTD treatment increases hole mobility by an order of magnitude and significantly improves the on/off ratio of transistors.
- BDTD-treated transistors show excellent reproducibility and stability without encapsulation.
- Integration with C60 transistors results in functional perovskite–C60 inverters for complementary logic applications.

## Abstract

Solution‐processed metal halide perovskite transistors possess intrinsic characteristics that hold promise for integration with n‐type semiconductors such as fullerene (C60) in CMOS‐like circuits. Yet, their performance and stability remain inferior to n‐type counterparts due to inefficient in‐plane charge transport and defect‐induced instabilities. This study proposes a rational additive engineering strategy using 4,8‐dihydrobenzo[1,2‐b:4,5‐b′]dithiophen‐4,8‐dione (BDTD) to regulate nucleation and crystallization of MA0.4FA0.6Sn0.5Pb0.5I3 films. BDTD alleviates microstrain, suppresses Sn4+‐related defects, and passivates undercoordinated Sn and Pb ions, forming smoother films with enlarged grains. Compared to control devices, the optimized transistor achieves an increase by an order of magnitude in hole mobility (4.1 vs. 0.38 cm2 V−1 s−1) and a substantially improved on/off ratio (1.8 × 105 vs. 3.1 × 104). Moreover, the BDTD‐treated transistors exhibit excellent reproducibility and operational stability under inert conditions without encapsulation. Furthermore, surface passivation using tetrabutylammonium hexafluorophosphate (TBAPF6) reduces interfacial traps, improving reliability and lowering the threshold voltage from 9.89 to 3.6 V. Finally, integration with an n‐type C60 transistor yields a functional perovskite–C60 inverter, demonstrating strong potential for complementary logic applications. This work highlights the synergistic role of additive and interfacial engineering in overcoming intrinsic limitations of Sn‐Pb perovskites, offering a viable pathway toward practical perovskite‐based complementary electronics.

An additive engineering strategy employing 4,8‐dihydrobenzo[1,2‐b:4,5‐b′]dithiophen‐4,8‐dione (BDTD) is utilized to passivate bulk defects, regulate crystallization dynamics, and suppress Sn4+ formation in Sn–Pb perovskite thin‐film transistors. The incorporation of BDTD yields a substantial enhancement in electrical performance, increasing the hole mobility from 0.38 cm2 V−1 s−1 (control) to 4.1 cm2 V−1 s−1 (BDTD‐treated) and improving the on/off ratio from 3.1 × 104 to 1.8 × 105.