A Joint Parallel Timing Recovery Loop with Low Complexity for Terahertz Communication System and Its FPGA Implementation

TL;DR

This paper introduces a low-complexity timing recovery system for terahertz communication that efficiently handles high-speed data with reduced hardware resources.

Contribution

A novel joint parallel timing recovery loop is proposed, enabling efficient high-speed THz communication with minimal hardware usage.

Findings

The proposed loop achieves less than 0.1 dB performance loss compared to theoretical BER curves.

It successfully demodulates 15 Gbps 64QAM signals at 220 GHz using an FPGA.

The design reduces hardware resource consumption in parallel THz communication systems.

Abstract

This paper proposes a low-complexity joint parallel timing recovery loop, which is well-suited for large-bandwidth terahertz (THz) communication systems. Specifically, the loop is jointly composed of a modified matched filter (MMF) and a timing error detector (TED), where sampling point offset correction is achieved by deleting, holding, or retaining data in parallel data caches (DCs), and timing phase error compensation is implemented by sliding the coefficients of the MMF. The feasibility of the proposed loop is verified using both Gardner and O&M TED. Numerical simulation results demonstrate that the loop operates efficiently, with a performance loss of less than 0.1 dB compared to the theoretical bit error rate (BER) curve. Furthermore, the loop is implemented on a THz field-programmable gate array (FPGA) platform, successfully realizing parallel demodulation of 15 Gbps 64QAM high-speed signals at 220 GHz. Notably, the proposed loop effectively reduces hardware resource consumption under a parallel architecture, providing a viable solution to address the current shortage of on-board resources in high-speed THz communication systems.

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