Stochastic Neuromorphic Computing Architecture Based on Voltage-Controlled Probabilistic Switching Magnetic Tunnel Junction (MTJ) Devices

TL;DR

This paper proposes a low-power neuromorphic computing architecture using magnetic tunnel junctions with voltage-controlled probabilistic switching for efficient edge computing.

Contribution

A novel voltage-controlled probabilistic switching MTJ device and its application in a low-power in-memory computing architecture for CNNs.

Findings

VCMA voltage pulses reduce spin Hall current density and pulse width, minimizing ohmic losses and Joule heating.

Voltage-controlled SHE-MTJ devices exhibit stochastic switching behavior with a sigmoidal voltage-probability response.

The proposed architecture achieves 72.49% Top-1 accuracy on CIFAR-10 with SqueezeNet and 1.25 × 10^6 parameters.

Abstract

As integrated circuits face increasingly stringent demands regarding power consumption, area, and stability, integrating novel spintronic devices with computing architectures has become a crucial direction for breaking through traditional computing paradigms. In the paper, switching mechanism of Magnetic Tunnel Junctions (MTJs) under the synergistic effect of Voltage-Controlled Magnetic Anisotropy (VCMA) and the Spin Hall Effect (SHE) is investigated. VCMA-assisted switching SHE-MTJ device is adopted, and a macrospin approximation model is established based on the Landau-Lifshitz-Gilbert (LLG) equation to systematically analyze its dynamic characteristics. The research demonstrates that applying VCMA voltage pulses with appropriate amplitude and width can significantly reduce the required spin Hall current density and pulse width for switching, thereby effectively minimizing ohmic losses and Joule heating. Furthermore, by incorporating a thermal fluctuation field, voltage-controlled SHE-MTJ device with stochastic switching behavior can be constructed, obtaining an approximately sigmoidal voltage-probability response curve. This provides an ideal physical foundation for stochastic computing and neuromorphic computing. Based on the above established fundamental discovery, an in-memory computing architecture supporting binarized Convolutional Neural Networks (CNNs) is proposed and designed in the paper. Combined with the lightweight network SqueezeNet, this architecture achieves a Top-1 recognition accuracy of 72.49% on the CIFAR-10 dataset, with a parameter count of only 1.25 × 106. This work offers a feasible spintronic implementation scheme for low-power, high-energy-efficiency edge-side intelligent chips.

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