# The Evolution of Lithography: From Resolution Scaling to Manufacturing Constraints

## TL;DR

This paper reviews the development of lithography techniques and explains why some promising methods fail to scale due to manufacturing constraints.

## Contribution

A decision framework is introduced to evaluate lithography methods based on manufacturing-relevant criteria.

## Key findings

- Traditional, non-conventional, and contemporary lithography techniques are analyzed for their scalability bottlenecks.
- Many emerging methods are limited by system-level factors like process windows and compatibility with existing ecosystems.
- The framework helps researchers align innovations with practical manufacturing needs.

## Abstract

Lithographic patterning continues to evolve under the dual pressure of ever-finer features and manufacturable, cost-effective integration. Beyond headline resolution, industrial adoption is increasingly determined by a small set of coupled metrics: throughput, overlay (registration), defectivity, and cost, as well as by how these trade-offs shift with materials, substrate form factors, and integration flows. Here, we review lithographic techniques across three eras: traditional methods (pre-1990s), non-conventional innovations (1990s), and contemporary advancements (post-2000s), with an explicit goal that goes beyond compilation. Specifically, we provide a decision framework for interpreting each method using the same manufacturing-relevant criteria. For each class of technique, we summarize the operating principle and representative process routes, then map the dominant bottlenecks to the metric that ultimately limits scale-up. This cross-cutting lens clarifies why many emerging methods are compelling at the physics level yet remain constrained at the system level, where process windows, in-line control, and compatibility with existing fabrication ecosystems govern viability. By connecting mechanism-level innovation to manufacturing-level constraints, this review offers practical guidance for researchers and engineers seeking to position nanolithography options for applications ranging from high-volume semiconductor production to agile prototyping and materials- or substrate-limited devices.