# Design of a Nanowatt-Level-Power-Consumption, High-Sensitivity Wake-Up Receiver for Wireless Sensor Networks

## TL;DR

This paper presents a highly efficient wake-up receiver for wireless sensor networks that uses very little power and can detect weak signals over long distances.

## Contribution

The paper introduces a novel wake-up receiver design with nanowatt-level power consumption and high sensitivity through event-triggered mechanisms and system-level innovations.

## Key findings

- The proposed wake-up receiver consumes only 305 nW at 0.5 V and achieves a sensitivity of −47 dBm.
- The design enables a communication range of up to 400 m in the 920–925 MHz band.
- The system-level innovations improve energy efficiency and reliability in wireless sensor networks.

## Abstract

This paper addresses the core conflict between long-range communication and ultra-low power requirements in sensing nodes for Wireless Sensor Networks (WSNs) by proposing a wake-up receiver (WuRx) design featuring nanowatt-level power consumption and high sensitivity. Conventional architectures are plagued by low energy efficiency, poor demodulation reliability, and insufficient clock synchronization accuracy, which hinders their practical application in real-world scenarios like WSNs. The proposed design employs an event-triggered mechanism, where a continuously operating, low-power WuRx monitors the channel and activates the main system only after validating a legitimate command, thereby significantly reducing standby power. At the system design level, a key innovation is direct conjugate matching between the antenna and a multi-stage rectifier, replacing the traditional 50 Ohm interface, which substantially improves energy transmission efficiency. Furthermore, a mean-detection demodulation circuit is introduced to dynamically generate an adaptive reference level, effectively overcoming the challenge of discriminating shallow modulation caused by signal saturation in the near-field region. At the baseband processing level, a configurable fault-tolerant correlator logic and a data-edge-triggered clock synchronization circuit are designed, combined with oversampling techniques to suppress clock drift and enhance the reliability of long data packet reception. Fabricated in a TSMC 0.18 µm CMOS process, the receiver features an ultra-low power consumption of 305 nW at 0.5 V and a high sensitivity of −47 dBm, enabling a communication range of up to 400 m in the 920–925 MHz band. Through synergistic innovation at both the circuit and system levels, this research provides a high-efficiency, high-reliability wake-up solution for long-range WSN nodes, effectively promoting the large-scale application of WSN technology in practical deployments.