# A reconfigurable photosensitive split-floating-gate memory for neuromorphic computing and nonlinear activation

## TL;DR

A new memory device integrates sensing, computing, and nonlinear functions for efficient AI hardware.

## Contribution

A reconfigurable split-floating-gate memory that unifies in-sensor, in-memory computing and nonlinear activation in one device.

## Key findings

- The device enables non-volatile analog control of photoresponsivity and conductance.
- It supports electrically reconfigurable rectification to emulate ReLU and Sigmoid activations.
- A hardware-implemented system using the memory performs unsupervised and supervised learning tasks.

## Abstract

The rapid growth of artificial intelligence and the Internet of Things calls for compact hardware platforms that integrate sensing, computing, and nonlinear processing within a unified architecture. However, most existing neuromorphic systems implement only partial functionalities and rely on heterogeneous device integration, limiting scalability and efficiency. Here, we show a high-speed, reconfigurable multi-modal split-floating-gate memory that monolithically integrates in-sensor computing, in-memory computing, and multiple nonlinear activation functions within a single device structure. By programming charges in spatially separated floating gates, the device enables non-volatile analog control of photoresponsivity and conductance, as well as electrically reconfigurable rectification to emulate ReLU and Sigmoid activations. We further demonstrate a fully hardware-implemented sensor–processor system based on the multi-modal split-floating-gate memory arrays that performs complete unsupervised and supervised learning tasks. This work establishes a compact, energy-efficient, and reconfigurable hardware foundation for scalable intelligent systems beyond conventional silicon architectures.

All-in-one computing, which merges sensing, linear computing, and nonlinear activation, is a critical goal for next-generation AI hardware. Here, Zhang et al. introduce a high-speed, reconfigurable split-floating-gate memory, enabling multi-function integration within a unified platform and hardware native neuromorphic processing.