# A Low-Noise and High-Integration Readout IC with Pixel-Level Single-Ended CDS for Short-Wave Infrared Focal Plane Arrays

## TL;DR

The paper introduces a new readout IC for SWIR focal plane arrays that reduces noise and improves integration density.

## Contribution

A compact, pixel-level single-ended CDS architecture is proposed to enhance SWIR detection performance.

## Key findings

- The proposed ROIC achieves a noise floor of 0.50 mV, a 70% reduction compared to conventional designs.
- The design supports both ITR and IWR modes with high linearity (0.9999) and low power consumption (<200 mW).
- Capacitor reuse optimizes the noise–area trade-off in high-density SWIR systems.

## Abstract

Improving sensitivity in short-wave infrared (SWIR) detection is crucial for low-signal applications, such as astronomy and hyperspectral imaging, which demand readout integrated circuits (ROICs) with minimal noise and high density. However, conventional differential pixels with correlated double sampling (CDS) are difficult to integrate due to spatial limitations. In order to tackle this issue, we propose a compact, pixel-level, single-ended charge-domain architecture. It integrates single-ended CDS within each pixel, guaranteeing compatibility with the integrate-while-read (IWR) mode while suppressing reset and 1/f noise. A capacitor reuse technique is also proposed to enable the integration capacitor to function as an auxiliary load, which optimizes the noise–area trade-off. Fabricated in 180 nm CMOS, our 1296 × 256 ROIC attains a noise floor of 0.50 mV (achieving a reduction of approximately 70% compared to conventional architectures under identical conditions), consumes under 200 mW, and operates at frequencies exceeding 200 Hz. It also exhibits great linearity (0.9999) and supports both integrate-then-read (ITR) mode and integrate-while-read (IWR) mode, while also providing a row-level gain selecting function. Validated at 15 μm pitch, this design provides an effective option for high-density SWIR systems.