# Co-field-reconciled direct growth of 6-inch monolayer graphene

## TL;DR

This paper introduces a new method to grow high-quality monolayer graphene on 6-inch sapphire wafers without transfer, enabling scalable and uniform production for electronic applications.

## Contribution

The co-field-reconciled strategy enables scalable and uniform growth of 6-inch monolayer graphene on insulators.

## Key findings

- The co-field strategy allows uniform growth of 6-inch monolayer graphene on sapphire with batch-production capability.
- The graphene produced shows high crystal quality, spatial uniformity, and electrical performance.
- The method can be extended to other insulating substrates like SiC, WC, Si3N4, and SiO2.

## Abstract

The transfer-free synthesis of inch-scale high-quality graphene on insulators is of paramount importance for emerging electronic and optoelectronic applications. Nevertheless, recent efforts at direct growth via the chemical-vapor-deposition route failed to produce monolayer graphene with a large wafer size (i.e. 6 inches) affording scalable uniformity and batch repeatability. Here, we report a co-field-reconciled synthetic strategy in which the synergistic optimization of thermal and gas-flow fields readily allows the uniform growth of 6-inch monolayer graphene over a sapphire wafer with batch-production capability. The temperature and flow fields are dictated via the concurrent deployment of a graphite gasket and a gas distributor plate, with the effectiveness evidenced by simulation and wafer-level characterization results. Theoretical calculations reveal that our route lowers the methane-decomposition barrier and restrains multilayer nucleation. The thus-prepared graphene exhibits impressive crystal quality, spatial uniformity and electrical performance. Six-inch wafer-scale top-gated graphene field-effect transistor arrays showcase the consistent device characteristics, with a room-temperature mobility average rivaling the state-of-the-art examples. The generality of such a route could be extended to other insulating substrates, including SiC, WC, Si3N4 and SiO2. This work achieves co-field optimization during wafer-level graphene growth over insulators and lays the foundation for advancing the large-scale integration of graphene.

This work reports the co-optimization of temperature and flow fields in a cold-wall chemical vapor deposition reactor, allowing monolayer graphene growth directly over 6-inch sapphire substrate toward wafer-level device integration.