Overcoming quadratic hardware scaling for a fully connected digital oscillatory neural network
Bram F. Haverkort, Aida Todri-Sanial

TL;DR
This paper introduces a digital oscillatory neural network design that scales efficiently, enabling a large number of connected oscillators with reduced hardware costs.
Contribution
A novel hybrid architecture for digital ONNs that achieves near-linear hardware scaling instead of quadratic.
Findings
The hybrid architecture achieves near-linear hardware scaling with a scaling factor of about 1.2.
The design allows a 10.5 × increase in oscillators on a Zynq-7020 FPGA using 5-bit and 4-bit representations.
The implementation includes 506 fully connected oscillators, the largest of its kind in digital ONNs.
Abstract
Computing with coupled oscillators or oscillatory neural networks (ONNs) has recently attracted a lot of interest due to their potential for massive parallelism and energy-efficient computing. However, to date, ONNs have primarily been explored either analytically or through analog circuit implementations. This paper shifts the focus to the digital implementation of ONNs, examining various design architectures. We first report on an existing digital ONN design based on a recurrent architecture. The major challenge for scaling such recurrent architectures is the quadratic increase in coupling hardware with the network size. To overcome this challenge, we introduce a novel hybrid architecture that balances serialization and parallelism in the coupling elements that shows near-linear hardware scaling, on the order of about 1.2 with the network size. Furthermore, we evaluate the benefits…
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Taxonomy
TopicsNeural Networks and Reservoir Computing · Ferroelectric and Negative Capacitance Devices · Neural Networks and Applications
