# Reducing Coercive Field and Improving Endurance in Ferroelectric Epitaxial Hf0.5Zr0.5O2 Thin Films via Novel Interface Layer Approach

## TL;DR

A new interface layer reduces the coercive field and improves endurance in ferroelectric HZO thin films for memory devices.

## Contribution

An ultrathin Sm-doped HZO underlayer enables redox-free switching and significantly enhances ferroelectric performance.

## Key findings

- Coercive field decreased by ≈25% from 3.3 to 2.5 MV/cm with the Sm-doped HZO underlayer.
- Endurance improved by an order of magnitude without compromising polarization.
- XPS and NEB calculations confirm reduced switching barriers and absence of redox effects in the interface layer.

## Abstract

Ferroelectric doped hafnium oxide (HfO2) has emerged as CMOS‐compatible and scalable ferroelectric for next‐generation memory/in‐memory computing devices. However, its high coercive field (Ec) and limited endurance remain key obstacles. Here, a ≈25% reduction in Ec from 3.3 to 2.5 MV/cm and an order of magnitude increase in endurance by implementing an ultrathin (≈2 nm) 5 at.% Sm‐doped HZO (HZSO) ionic conducting underlayer for HZO are shown. X‐ray photoelectron spectroscopy (XPS) results reveal the absence of redox effects during primary ferroelectric switching in HZSO, unlike in HZO. NEB calculations show that VO‐rich HZSO lowers the switching barrier compared to that of HZO, which agrees with experimental results. Notably, these improvements are achieved in HZSO|HZO without compromising Pr compared to HZO. This approach presents a new powerful route to engineering ferroelectric properties in doped HfO2, applicable to both epitaxial and polycrystalline films for future memory devices.

An ultrathin samarium doped hafnium zirconium oxide (Sm:HZO) underlayer reduces coercive field by ∼25% and enhances endurance tenfold in epitaxial ferroelectric HZO overlayer. The Sm:HZO interface allows redox mitigated oxygen exchange and lowers switching barriers, achieving stable polarization with enhanced endurance performance. This interfacial engineering strategy offers a scalable route for low power ferroelectric memory applications.