# Analog Front-End ASIC for Compact Silicon Photomultiplier Sensor Interfaces in Mixed-Signal Systems

## TL;DR

This paper introduces a compact, mixed-signal ASIC designed to interface with Silicon Photomultiplier sensors for efficient and precise photon detection.

## Contribution

The novel contribution is a custom ASIC with optimized current conveyors and a behavioral SiPM model for improved signal detection and timing.

## Key findings

- The ASIC achieves 5.9 mA power consumption at 3.3 V with stable operation across the dynamic range.
- Custom CCII+ and discriminator blocks enable low-impedance current reception and fast signal processing.
- A 10-bit current-mode DAC provides fine-grained bias and threshold control with 200 nA resolution.

## Abstract

We present a mixed-signal front-end ASIC designed for compact Silicon Photomultiplier (SiPM) sensor interfaces, implemented in the AMS 0.35 µm CMOS technology. The chip integrates two independent analog channels, each composed of five custom second-generation current conveyors (CCII+), a fast zero-crossing discriminator, and a peak-and-hold stage based on a tailored operational amplifier. The CCII+ and discriminator blocks were designed in-house, based on literature designs and adapted to the technology to ensure low input impedance and fast current-mode signal propagation. This architecture enables precise detection of small signals with reduced pile-up, important for time-resolved photon detection. Bias and threshold control are provided by programmable current mirrors and SPI-configurable DACs, including a 10-bit current-mode DAC based on a current-splitting structure with approximately 200 nA resolution. A custom SiPM behavioral model was developed in the Cadence environment to support design and simulation, reproducing realistic pulse shapes and recovery dynamics for timing applications. Circuit-level simulations confirm correct analog functionality and stable operation across the intended dynamic range, with a per-channel consumption of about 5.9 mA at 3.3 V (19.5 mW), reflecting a tradeoff between speed and robustness. The system is compatible with external timing architectures, while internal CCII+ stages ensure low-impedance current reception, fast discrimination, and accurate current-to-voltage conversion for peak detection.