# Advancements in Active-Pixel-Type CMOS Image Sensor Design Techniques and Architectures for Wide Dynamic Range

## TL;DR

This paper reviews design techniques for CMOS image sensors to achieve wide dynamic range, useful for applications like machine vision and IoT.

## Contribution

The paper provides a comprehensive overview of active-pixel-type CIS architectures and techniques for enhancing wide dynamic range.

## Key findings

- Multiple exposure and dual conversion gain schemes help address trade-offs in CIS performance.
- LOFIC and dual photodiode architectures improve dynamic range through optimized exposure mechanisms.
- Logarithmic and Lin-Log CIS responses enable non-linear characteristics for better image capture.

## Abstract

Advances in CMOS image sensors (CISs) have led to utilization in various industrial fields, including machine vision, medical, surveillance, the automotive industry, and the Internet of Things (IoT). One critical metric for CISs is the dynamic range (DR), which indicates the range of light intensity that can clearly capture images. As the technology evolves, wide dynamic range (WDR) becomes increasingly required for more diverse applications. To further advance these industries, this paper presents the active-pixel-type CIS design techniques and architectures developed to achieve WDR. These include the following: the basic concepts of the active pixel sensor, readout mechanism, and DR of the CIS; multiple exposure and dual conversion gain (DCG) schemes that are conventionally used to address a trade-off in the CIS; lateral overflow integration capacitor (LOFIC) and dual photodiode (PD) architectures that can improve the DR by utilizing trade-offs in the DR and exposure mechanism; CISs with logarithmic and linear–logarithmic (Lin-Log) responses to enable non-linear characteristics; and techniques that can be employed for higher sensitivity in dark conditions. This comprehensive study of various techniques and architectures can also be utilized for cutting-edge tech advances and future research, including neuromorphic array architecture.