Device and Circuit Co-Optimization of Split-Controlled Flip-Flops Against Aging Towards Low-Voltage Applications

TL;DR

This paper presents a new method to improve the reliability of low-voltage circuits by reducing aging effects in a specific type of flip-flop.

Contribution

A novel transistor-level mitigation technique is proposed for Split-Controlled Flip-Flops in low-voltage applications.

Findings

The improved SCFF reduces PMOS threshold voltage degradation by over 60%.

Timing delay is reduced by 40% while maintaining operation at 0.4 V.

The method enhances reliability in low-voltage circuits affected by aging.

Abstract

The continued downscaling of transistors has exacerbated aging mechanisms such as bias temperature instability (BTI) and hot-carrier injection (HCI), posing significant reliability challenges for nanoscale integrated circuits. These effects are particularly critical to flip-flops operating at low supply voltages, which are essential for ultra-low-power applications including the Internet of Things (IoT) and biomedical implants. In this work, we address the aging issue in low-voltage Split-Controlled Flip-Flops (SCFFs) by proposing a novel transistor-level mitigation technique specifically tailored to this architecture within a domestic 14 nm process library. Through a detailed analysis of aging-critical transistors, three targeted enhancement strategies are introduced. Simulation results demonstrate that the improved SCFF achieves more than a 60% reduction in PMOS threshold voltage degradation and a 40% reduction in timing delay, while maintaining robust operation at a supply voltage as low as 0.4 V. These results highlight the effectiveness of the proposed approach in mitigating aging effects and enhancing reliability under low-voltage operation.

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