# Evaluation of TRNG Bit Distribution via Stable Entropy Source Synchronization on FPGA

## TL;DR

This paper evaluates how using multiple delay flip-flops improves the randomness of numbers generated by ring oscillators on FPGA.

## Contribution

The study introduces multi-D-FF synchronization circuits to enhance bit distribution in RO-based RNGs.

## Key findings

- Using two or more D-FFs after RO signals improves bit distribution.
- Metastable states in XOR gate inputs affect overall bit distribution.
- NIST tests confirmed improved randomness with the proposed synchronization method.

## Abstract

This study examined the correlation between the number of delay flip-flops (D-FFs) connected after each ring oscillator (RO) and the bit distribution of random number sequences in an RO-based random number generator (RNG). In our previous research, unstable input signals to the XOR gate contributed to differences in bit distribution. Based on these results, we simulated how combining signals with biased distributions through XOR gates affects the overall bit distribution. Beyond this, we also conducted simulations where the inputs to the XOR gate included not just {0, 1} signals, but also three-state signals incorporating metastable states. We then proposed using multi-D-FFs as synchronization circuits for RO signals and performed analyses on RO-based RNG implementations by estimating metastable output conditions and conducting NIST Special Publication 800-22 tests regarding bit distributions. These results confirm that inserting two or more D-FFs after RO signals improves the bit distribution of RO-based RNG implementations.