A new 37- level inverter with reduced switches for renewable energy applications

TL;DR

This paper introduces a new 37-level inverter with fewer switches, offering high efficiency and low distortion for renewable energy and electric vehicle systems.

Contribution

A novel 37-level inverter topology with reduced switches and improved performance metrics for renewable energy applications.

Findings

The inverter achieves a THD of 1.21% in hardware and 0.8% in simulation.

It demonstrates 93.26% efficiency and reduced standing voltage of 18 VDC.

The design is validated through simulations and a laboratory prototype under varying loads.

Abstract

Multilevel inverters (MLIs) are now crucial in producing high-quality output waveforms due to their modularity and efficiency. This paper presents a novel 37- level MLI topology with a reduced number of switches and sources. The proposed design offers several advantages, including lower total harmonic distortion (THD) of 1.21% in hardware and 0.8% in simulation, high efficiency of 93.26%, reduced total standing voltage of 18 VDC), and an improved component-per-level ratio compared to existing MLIs. The inverter performance is validated using MATLAB/Simulink and a laboratory prototype controlled by a dSPACE system under different load conditions. Results confirm that the proposed inverter maintains stable operation during dynamic load changes and provides a cost-effective, compact, and reliable solution for renewable energy and electric vehicle applications.

Figures

Parameter-based comparisons of the proposed 37- level MLI.

Novel 37- level MLI.

Simulation THD of MLI.

Laboratory Set-up.

Hardware results of 37- level MLI, (a) output voltage waveform. (b) R load results (c) Motor load results, (d) Dynamic RL load changes, (e) Dynamic LR load changes, and (f) Levels Vs MI.

Simulation THD of MLI.

Laboratory Set-up.

Hardware results of 37- level MLI, (a) output voltage waveform. (b) R load results (c) Motor load results, (d) Dynamic RL load changes, (e) Dynamic LR load changes, and (f) Levels Vs MI.

Experimental THD of the suggested MLI.

Full text

Introduction

The multilevel inverter (MLI) topologies such as CHB, NPC, and FC have been developed still face challenges like increased switch count, complex control, and higher total standing voltage (TSV) at higher levels. These issues lead to reduced efficiency, reliability, and cost-effectiveness. To overcome these limitations, the proposed asymmetric 37-level inverter achieves more voltage levels using fewer switches and reduced TSV, thereby enhancing efficiency and lowering THD for renewable and electric vehicle applications^1^. The applications of PV systems in a plethora of applications such as grid electricity generation, electric vehicles (EVs), and power distribution in industry have generated the demand for efficient power conversion technology^2–4^. One of the most vital parts of the process is the inverter that enables the power conversion of the DC electricity generated by solar PV panels into AC electricity compatible with contemporary electrical loads and aircraft applications^5,6^. Nevertheless, for high-power applications, traditional voltage source inverters (VSIs) efficiency and reliability are hampered by serious drawbacks such as high switching losses, high total harmonic distortion (THD)^7,8^, and high electromagnetic interference (EMI)^9^. Multilevel inverters (MLIs) have been recognized to be the better alternative to these challenges with higher power quality, lower switching stress, and higher efficiency; therefore, they are a choice for power conversion in industrial and renewable energy applications^10–15^.

Baker and Bannister initially developed multilevel inverters in the 1970 s to enhance power conversion efficiency using multiple DC sources and semiconductor switches to generate stepped voltage waveforms^16^. Numerous different MLI topologies have been suggested since then, including the cascaded H-Bridge (CHB)^17–19^, neutral-point clamped (NPC)^20–22^, and flying capacitor (FC) configurations^23–25^. Due to its modularity, scalability, and minimal dependence on high-power semiconductor switches, the CHB-MLI has been the most widely used among them^26^. CHB-MLIs are highly efficient for high-power applications since they do not need extra voltage-balancing components, unlike NPC-MLIs, which need clamping diodes to provide voltage balance between series-connected capacitors^10–28^. While NPC-MLIs have improved voltage sharing, their high voltage-level complexity makes them susceptible to operational disadvantages such as non-uniform voltage stress distribution among power devices^29^. FC-MLIs with floating capacitors rather than diodes to balance voltage also need a lot of capacitors, making them unsuitable for high-voltage applications. The largest drawback of traditional MLIs, despite their benefits, is that they do not handle the growing number of components as output voltage levels increase. Higher-level MLIs require more isolated DC sources, gate driver circuits, and semiconductor switches, which increases system cost, switching losses, and control approach complexity^30–32^.

To overcome these limitations, researchers have investigated asymmetric MLI topologies that employ non-equal DC voltage sources to obtain maximum voltage levels with fewer switches and passive components^33^. This design method increases cost-effectiveness, efficiency, and system compactness, and therefore asymmetric MLIs are ideal for power applications in the present time^34^. Asymmetric MLIs can generate the same or even greater voltage levels with fewer components than symmetric MLIs, which employ equal DC voltage sources and additional switches to generate different voltages. According to research, asymmetric configurations greatly reduce conduction losses and total standing voltage (TSV), increasing MLIs’ power efficiency and harmonic reduction capability^35^. more MLI structures emphasizing lower semiconductor stress, lower cost, and higher operating reliability are the outcome of the increased demand for power electronic systems to be optimized^36–41^.

To meet these changing needs, this paper introduces a new 37-level asymmetrical MLI with improved efficiency, reduced total harmonic distortion, reduced semiconductor switches, and reduced total standing voltage. The new topology utilizes five asymmetrical DC sources, four bidirectional switches, and eight unidirectional switches, which together provide a high-efficiency, low-cost solution with low THD. In comparison with traditional MLI topologies, the proposed 37-level inverter has some benefits, such as enhanced power quality, reduced semiconductor usage, and enhanced efficiency, which makes it a suitable candidate for high-power applications. The proposed topology minimizes TSV by utilizing an optimal switch and source configuration, which minimizes the stress on semiconductor devices and enhances system reliability. Moreover, the stepped output waveform provides less harmonic distortion, which eliminates the need for complex filtering devices and enhances the overall efficiency of the inverter. An optimized control scheme also allows the inverter to provide a constant voltage output even when loads change, which makes it more appealing for electric car power systems, industrial motor drives, and renewable energy integration^42–44^.

The new 37-level inverter is contrasted with traditional MLI topologies on key parameters like THD, TSV, efficiency, and power loss for comparison of its performance. Simulation is carried out to analyze its efficiency, and the design is also experimented to check its viability for applications. Findings show the superiority of the new MLI as a future device for high power conversion efficiency with reduced harmonic distortion. Breaking the limitations of traditional MLIs, this research provides a new boost to the development of power electronics and its applications to electric vehicle charging, renewable energy integration, active power filtering, and uninterruptible power supplies. The 37- output levels were obtained with four bidirectional & eight unidirectional switches, as discussed^45^. The bidirectional switch \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{S}_{c}$$\end{document} can be replaced with a unidirectional switch to generate the same output levels.

Recent study has investigated reduced-component and switched-capacitor-based MLI to improve efficiency and reduce device count. Debela et al.^46^ proposed a grid-connected boost multilevel inverter (BMLI) with a simplified configuration, achieving enhanced performance in renewable energy applications. Furthermore^47^, Evaluated an H-bridge-less grid-tied inverter emphasizing minimized TSV. These works support the growing trend toward optimized MLIs, which motivates the development of the proposed 37-level inverter with further reductions in TSV, THD, and switch count. These advancements reinforce the need for novel inverter designs with reduced switch count and improved harmonic performance, which motivates the proposed 37-level inverter presented in this work.

In the realm of solar PV energy systems, these advancements are pivotal, enhancing the capacity and efficiency of Electric Vehicles (EVs) and FACTS. The proposed 37 level MLI architecture, detailed in this paper, is accompanied by comprehensive circuit schematics and switching tables in Sect. 2. Sect. 3 presents a comparison of simulated and measured results from hardware implementations. Sect. 4 evaluates parameters such as TSV, cost-efficiency, power losses, and overall system efficiency. Finally, Sect. 5 discusses the implications of these findings and outlines avenues for future research.

The novelty of the proposed work lies in the development of an asymmetric 37-level multilevel inverter (MLI) topology that achieves a significant reduction in switch count, total standing voltage (TSV), and harmonic distortion, while maintaining high efficiency. Compared to existing topologies, the design uniquely balances performance and economic feasibility with only 12 switches (including 4 bidirectional), 5 unequal DC sources, and reduced component-per-level ratio. The inverter’s performance is validated through both simulation and hardware using dSPACE RTI 1104, highlighting its practical applicability for renewable energy and EV systems.

Proposed asymmetrical 37-Level MLI topology

The proposed MLI with reduced components is presented in Fig. 1, which features three bidirectional and eight unidirectional switches to achieve the maximum possible output levels.

Fig. 1. Novel 37- level MLI.

The selection of components as follows:

The general cells (m) & supply sources (n) are required to estimate the parameters of the proposed architecture.

The sources \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{(R}_{DC})$$\end{document} can be evaluated with unequal sources combination

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{\:R}_{DC}={1+2}^{m}$$\end{document}

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{R}_{DC}$$\end{document} is obtained with Eq. (1)

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{R}_{DC}={1+2}^{2}=1+4=5$$\end{document}

The number of voltage levels (V_PL_) is calculated

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{V}_{PL}=1+{6}^{m}$$\end{document}

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{V}_{PL}$$\end{document} can be obtained with Eq. (2)

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{V}_{PL}={1+6}^{2}=1+36=37$$\end{document}

The required switches (RSW) can be estimated

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{R}_{SW}={4}^{m}-4$$\end{document}

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{R}_{Sw}$$\end{document} is designed with Eq. (3)

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{R}_{Sw}={4}^{2}-4=12$$\end{document}

The magnitude is designed

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{V}_{po}=\frac{\left[{6}^{m}+1\right]+1}{2}\mathrm{*}Rdc$$\end{document}

The voltage is estimated with Eq. (4)

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{V}_{po}=\frac{\left[{6}^{2}+1\right]+1}{2}\mathrm{*}22.5=405\:V$$\end{document}

Where m = 2 and source voltage are \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:22.5V$$\end{document} .

Using the equations mentioned above, the estimated components are designed for the proposed MLI. It can be extended to increase the various voltage levels with different voltage source combinations. Figure 1 shows a newly developed 37- level with reduced circuit power sources and switches for the generation of required high-quality output waveforms. The equal power sources such as \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{V}_{a}\to\:{V}_{b}\to\:{V}_{c}\to\:22.5V={R}_{dc}$$\end{document} , \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{V}_{d}\to\:157.5=7{R}_{dc}$$\end{document} and \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{V}_{e}\to\:180V=8{R}_{dc}$$\end{document} with values of resistance and inductor \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:100\:\varOmega\:,\:150\:mH,\:and\:200\:mH$$\end{document} respectively are implemented. The switches \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{S}_{D}\to\:{S}_{B}\to\:{S}_{A}$$\end{document} allow the current path for both the directions and \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{S}_{8}\to\:{\to\:S}_{7}\to\:{\to\:S}_{6}\to\:\to\:{S}_{5}\to\:\to\:{S}_{4}\to\:{\to\:S}_{3}\to\:\to\:{S}_{2}\to\:\to\:{S}_{1}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\to\:\to\:{S}_{c}$$\end{document} will conduct in only one direction. The required conduction of states is given in Table. I and its expected stepped voltage output waveform is shown in Fig. 2(a).

Fig. 2(a). Expected stepped voltage output waveform (b). Switching Sequence generation.

Although the switching sequence involves multiple states, the overall circuit offers clear benefits in terms of reduced TSV, lower switch count per level, and improved efficiency. The control strategy can be readily implemented on digital platforms such as dSPACE, making the added switching complexity acceptable for practical applications.

The proposed topology’s control strategy is implemented using a level-shifted Pulse Width Modulation (PWM) technique. A dSPACE RTI 1104 controller is used to generate PWM signals based on real-time load sensing. The modulation strategy ensures proper switching of unidirectional and bidirectional switches to synthesize the desired 37-level output. Figure 2(b) shows the switching Sequence generation of the modulation control implemented. The logic gate-based system that uses timing signals from the comparator to generate pulses in accordance with switch operation criteria. These logics are essential for transforming time signals into a logic pattern that the switch operates to produce.

The Table 1 is a switching table which guides the selection of switches for each voltage level.

Table 1. Proposed 37- MLI switch conduction.LSwitch conduction directions^‘^S_A_^’^^‘^S_B_^’^^‘^S_C_^’^^‘^S_D_^’^^‘^S_1_^’^^‘^S_2_^’^^‘^S_3_^’^^‘^S_4_^’^^‘^S_5_^’^^‘^S_6_^’^^‘^S_7_^’^^‘^S_8_^’^L1^‘^↓^‘^↓^‘^→^‘^↓L2^‘^→^‘^↓^‘^→^‘^↓L3^‘^→^‘^↓^‘^→^‘^↓L4‘↓^‘^↓^‘^→^‘^↓L5^‘^→^‘^↓^‘^→^‘^↓L6‘→^‘^↓^‘^→^‘^↓L7‘↓^‘^↓^‘^→^‘^↓L8←^‘^^‘^↓^‘^↓^‘^↓L9‘→‘↓^‘^→^‘^↓L10^‘^→^‘^→^‘^→^‘^↓L11^‘^→^‘^→^‘^→^‘^↓L12^‘^→^‘^↓^‘^→^‘^↓L13^‘^→^‘^→^‘^→^‘^↓L14^‘^→^‘^→^‘^→^‘^↓L15^‘^→^‘^↓^‘^→^‘^↓L16^‘^↓^‘^→^‘^→^‘^↓L17^‘^→^‘^→^‘^→^‘^↓L18^‘^→↓^‘^→^‘^↓L19^‘^↓↓^‘^→^‘^↓L20^‘^→‘→‘→^‘^↓L21^‘^→^‘^↓^‘^→^‘^↓L22^‘^↓^‘^↓‘→^‘^↓L23←’↓^‘^^‘^→^‘^↓L24^‘^→←’^‘^→^‘^↓L25^‘^→←’^‘^→^‘^↓L26←’^‘^↓‘→^‘^↓L27^‘^→←’‘→^‘^↓L28→^‘^→‘→‘↓L29^‘^→^‘^→‘→‘↓L30^‘^→↓‘→^‘^↓L31^‘^↓^‘^→‘→^‘^↓L32^‘^→‘→‘→‘↓L33^‘^→‘→‘→‘↓L34^‘^↓‘→‘→‘↓L35^‘^→‘→‘→‘↓L36^‘^→‘→‘→‘↓L37^‘^↓^‘^→‘→‘↓^‘^→ indicates the direction of the conducting switch & ‘L’ is levels.

The maximum peak voltage will be generated with all active sources are.

In state-1: 405 V, + 18V_DC_, the current flows as follows: V_a_-S_1_-S_4_-V_e_-V_d_-S_5_-L-S_8_-V_c_-V_b_-V_a_, as shown in Fig. 3. All DC sources are utilized to power the circuit (V_a_ +V_b_ + V_c_ + V_d_ + V_e_). For the purpose of creating extra positive voltages and zero voltage levels, the load current Io flows via a sequence of switches S_1_, S_4_, S_5_, and S_8_. Similar to state-19: 0 V, 0V_DC_, none of the sources (V_a_, V_b_, V_c_, V_d_, and V_e_) are supplying DC power to the system. Thus, L-S_8_ - S_2_ - S_4_ - S_6_ - L is the wiring path for the load current Io. A negative voltage of −2V_DC_ is generated when all seven of the S_B_, S_4_, S_6_, and S_7_ are active in state-21: −45 V operation, and the load current Io follows the following conductor path: L-S_6_ -S_4_ - S_B_ - V_b_ - V_a_ - S_7_ - L.

Fig. 337- MLI current paths.

3. Results analysis

V_DC_=V_a_=V_b_=V_c_=22.5 V, V_d_=157.5 V, and V_e_=180 V are the input DC sources that are used to test the architecture for the proposed MLI that is being used. The waveforms of the voltage and current outputs from MATLAB Simulink are plotted in Fig. 4(a-d) in the appropriate order. As shown in Fig. 4(a), the peak voltage is 405 V, the load current is 4.05 A, and the resistance of the load is shown to be 100 Ω. For the resistive load of 100 Ω and the inductive load of 150 mH, the output voltage (Vo) and current (Io) are shown in Fig. 4(b) and (c), respectively. In Fig. 4(d) and Fig. 4(e), the output voltage levels are depicted for a variety of modulation index (Ma) values. Furthermore, the THD yield is 0.80%, as can be seen in Fig. 5. The load, switching frequency, reference frequency, and DC voltage sources that are recommended for the architecture are all presented in Table 2.

Fig. 437- level MLI. (a) Output voltage (Vo), (b) R Load (Vo & Io), (c) L Load (Vo & Io), (d) Simulation output voltage of Modulation Index vs. Output Voltage and (e) Modulation Index vs. No. of Levels.

Fig. 5. Simulation THD of MLI.

Table 2. Specifications of the components.Components/ParametersRatings/TypeDriver CircuitTLP250R-load100 ΩSwitching frequency2000 HzDC sources500 V/ProgrammableIGBTs600 V,75 A/(CM75DU-12 H)dSPACE ControllerRTI 1104Reference frequency50 Hz

A working model of an experimental setup for a 37- level MLI configuration has been created and validated. Figure 6 shows the experimental setup for the 37- level inverter architecture that has been presented. An experimental kit prototype is utilized to implement the required configuration using dSPACE RTI 1104. The THD value of 0.80% corresponds to simulation under ideal conditions; the hardware prototype (Fig. 7) yields a measured THD of 1.21%, which validates the proposed design under practical operation.

Fig. 6. Laboratory Set-up.

Fig. 7. Hardware results of 37- level MLI, (a) output voltage waveform. (b) R load results (c) Motor load results, (d) Dynamic RL load changes, (e) Dynamic LR load changes, and (f) Levels Vs MI.

The experimental setup includes opto-isolated gate driver circuits (TLP250) with dead-time insertion to prevent shoot-through. Heat sinks and thermal paste were applied to high-power IGBTs for thermal protection. The system design also considers scalability, where the modular DC source configuration allows extension to higher voltage levels without modifying the control structure.

The recommended configuration was tested in MATLAB/Simulink before being sent to the dSPACE controller via digital I/O ports. It worked well thereafter. The gate driver enhances the PWM circuit’s design and can operate on voltages ranging from 4 to 16 V. The power semiconductor switches are activated utilizing a 15-volt pulse. Figure 8 displays the hardware’s results from the resistive load testing. The Fig. 8(a) & 7(b) is representing the prototype results of R load with 405 V output voltage and load current I_0_ = 4.05 A. The Fig. 8(c), (d) &€ shows the output current lags behind the output voltage of inverter (V_0_ = 405 V & I_0_ = 6.8 A) and output levels vs. modulation index is presented in Fig. 8(f). The voltage THD is 1.21%, as displayed in Fig. 7.

Fig. 8. Experimental THD of the suggested MLI.

Table 3. Proposed inverter experimental and simulation results comparisons.ParameterSimulationOutcomeHardwareOutcomeOutput Voltage (V_o)_405 V405 VOutput Current (I_o)_4.05 A4.05 ATHD0.80%1.21%

`The measured voltage THD is 1.21%, as indicated in Table 3. In accordance with IEEE standards, the suggested configuration can produce a scalable voltage level with minimal components and THD.

Estimation and comparison of the proposed MLI performance parameters

Estimation of total power losses (Ptotal loss) and efficiency (η%)

Conduction losses (PCDi) and switching losses (PSW) are two examples of the power losses that inverters mostly have to deal with. Taking into account the losses in the current conduction state of the switch IGBT (PIGBT) and the anti-parallel diode (PADi) yields net amount of conduction losses, which are represented as

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{{P}_{CDi}\left(\mathrm{t}\right)=\mathrm{P}}_{\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}\left(t\right)+{P}_{ADi}\left(t\right)$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{{P}_{CDi}\left(\mathrm{t}\right)=\left\{\right[\mathrm{V}}_{\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}+{R}_{DI}{i}_{n}^{\beta\:}\left(t\right)]+[{V}_{DI}+{R}_{DI}{i}_{n}\left(t\right)\left]\right\}{i}_{n}\left(t\right)$$\end{document}

The threshold voltages of switch (VIGBT), current (in), and on/off switch (in) are represented below. Given that the switches (NIGBT) & diodes (NDi) are activated at the same time intervals (t), where RIGBT and RDI denote the on-state resistance of the IGBT and diode, respectively, and \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\:\beta\:\:$$\end{document} stands for the switch constant. The power loss on average as follows

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{{P}_{CDi}=\frac{1}{2\pi\:}{\int\:}_{0}^{2\pi\:}\left\{{N}_{IGBT\:}\right(t)\mathrm{P}}_{\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}\left(t\right)+{N}_{Di}\left(t\right){P}_{ADi}\left(t\right)\}dt$$\end{document}

The energy losses that occur during power consumption include energy turn-on (E_on_) and turn-off (E_off_) for IGBT turn-on and off states.

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{E}_{off-time}=\frac{1}{6}\:{V}_{IGBTj}I{t}_{off}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{E}_{on-time}=\frac{1}{6}\:{V}_{IGBTj}{I}^{{\prime\:}}{t}_{on}$$\end{document}

The loss in switch is j, the ton & toff are the turn–on/off, Eoff−time and E_on−time,,_I & I’ of the switches respectively.

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{P}_{SW}=f\left\{\sum\:_{j=1}^{{N}_{IGBT}}{\left[\sum\:_{j=1}^{{N}_{on-time\:j}}{E}_{on-time\:j}+\sum\:_{j=1}^{{N}_{off-time\:j}}{E}_{off-time\:j}\right]}_{\:}\right\}$$\end{document}

The Non−time j and Noff−time j are the switch turn-on/off j^th^ time intervals with fundamental (f) with complete cycle.

The inverter’s complete Power losses (Ptotal losses) is estimated^47^

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{{P}_{Total\:losses}={P}_{CDi}+P}_{SW}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{P}_{outp}={V}_{rms}\mathrm{*}{I}_{rms}$$\end{document}

The inverter’s overall efficiency (η%) is obtained

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\eta\:\left(\mathrm{\%}\right)=\frac{{P}_{outp}}{{P}_{inpp}}=\frac{{P}_{outp}}{{P}_{outp}+{P}_{Total\:losses}}$$\end{document}

The inverter’s output and input powers are denoted by Poutn and Pinpp, respectively. Table 4 has a detailed discussion of the power losses and efficiency values that were determined.

Table 4. List of power loss calculations of the proposed MLI.Voltage (V_rms_)286.42 VR-load100 ΩCurrent (I_rms_)2.86 ASwitching losses (PSW)0.046 WConduction losses (P_CDi*)*4.89 WTotal losses (PTotal losses*)*59.23 WOutput power (Poutn*)*819.16 WInput power (Pinpp_*)*878.36 WEfficiency (% η)93.26

Total standing voltage (TSV) Estimation

A representation of the voltage that is being blocked is the ‘pressure’ that is across the switch. “Unidirectional” and “bidirectional” switches have different “voltage strains,” which means that they are not the same. The maximum output voltage is calibrated to 405 V when the highest performance level (V_0 MAX_) is used. The presented inverter, the equivalent voltages of the complementary switches are not comparable to one another. This is because the MLI makes use of four bidirectional switches and eight unidirectional switches. Accordingly, TSV can be obtained by using Eq. (14).

Total standing voltage (TSV) = 2(V_SA_+ V_SC_) + V_S1_ + V_S3_+ V_S6_ + V_S8_)

= 18V_dc_

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{TSV}_{PU}=\frac{{V}_{TSV}}{{V}_{OMAX}}$$\end{document}

The MBV can be obtained and given below:

MBV_S1_ = MBV_S2_ = MBV_S7_ = MBV_S8_ =3V_dc_.

MBV_S3_ = MBV_S4_ = MBV_S5_ = MBV_S6_ =15V_dc_.

MBV_SA_ = MBV_SB_ =3V_dc_.

MBV_SC_= MBV_SD_=15V_dc_.

The “Normalized voltage stress (NV_strs_)” refers to the ratio of V_strs_ across the IGBT switch to the maximum voltage V_L, max_^31^, given by

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$N{V_{strs}} = \frac{{{\bf{Vstrs}}}}{{{\bf{VL}},{\bf{max}}\:}}$$\end{document}

Where V_strs_ is real voltage stress of the IGBT switch & the values are given in Table 5. The IGBT Switches S_l_, S_2_, S_7_, S_8_, S_A_, and S_B_ experience the lowest V_strs_ and NV_strs_, i.e. 3V_dc_ and 16.66% respectively, whereas switches S_3_, S_4_, S_5_, S_6_, S_C_, and S_D_ experience the highest V_strs_ and NV_strs_, i.e. 15V_dc_ and 83.33%.

Table 5. Across power switches, voltage and normalized voltage stress.SwitchVoltage Stress (V_strs_)Normalized Voltage Stress (NV_strs_)S_1_3V_dc_.(3V_dc_./18V_dc_) = 16.66%S_2_3V_dc_.(3V_dc_./18V_dc_) = 16.66%S_3_15V_dc_.(15V_dc_./18V_dc_) = 83.33%S_4_15V_dc_.(15V_dc_./18V_dc_) = 83.33%S_5_15V_dc_.(15V_dc_./18V_dc_) = 83.33%S_6_15V_dc_.(15V_dc_./18V_dc_) = 83.33%S_7_3V_dc_.(3V_dc_./18V_dc_) = 16.66%S_8_3V_dc_.(3V_dc_./18V_dc_) = 16.66%S_A_3V_dc_.(3V_dc_./18V_dc_) = 16.66%S_B_3V_dc_.(3V_dc_./18V_dc_) = 16.66%S_C_15V_dc_.(15V_dc_./18V_dc_) = 83.33%S_D_15V_dc_.(15V_dc_./18V_dc_) = 83.33%

As shown in Fig. 9 (a), Each switch’s stress distribution is illustrated, while Fig. 9 (b) illustrates the normalised voltage stress expressed as a percentage, and Fig. 9 (c) illustrates the voltage limitations that are present in each level of the suggested topology.

Fig. 9(a) Distribution of voltage stress, (b) % in normalized voltage stress, and (c) Each level’s switches are subject to voltage limitations.

Assessment of the cost function (CF)

The proposed MLI structure’s estimated cost could be affected by a wide range of factors. The sum of all diodes (N_Dio_), switches (N_Swi_), driver circuits (N_Driv_), and sources (N_DS_) is included in this tally. Because of this, the cost component can be figured out by using the following relationship^26^.

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:CF=\:{(N}_{Swi}+{N}_{Dio}+{N}_{Cap}+\:{N}_{DS}+{N}_{Driv}+\alpha\:{TSV}_{PU})$$\end{document}

The weight factor ‘α’ is multiplied by the product of ‘TSVpu’. The CF can be calculated by using Eq. (17).

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:CF=\:{(N}_{Swi}+{N}_{Driv}+{N}_{DS}+\alpha\:{TSV}_{PU})$$\end{document}

In the majority of instances, the number ought to be greater than 1, even though it ought to be less than 1. To determine the ideal cost factor, the suggested value will be evaluated as 0.5 and 1.5, correspondingly. This will be done to determine the optimal cost factor. According to the computations of the number of components (CF/L), it has been discovered that the MLI is economically possible; the value for CF/level = 0.5 is 1.62, and the value for CF/L = 1.5 is 3.18. Both of these values are based on the MLI. By utilizing Eq. (18), one can determine the component count for each level factor.

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{\text{FCC/L = }}\frac{{({N_{Swi}} + {N_{DS}} + {N_{Cap}} + {N_{Dio}} + {N_{Driv}})}}{{Number\:of\:Levels}}$$\end{document}

Cost evaluation

To find the larger cost-benefit of using the suggested MLI for lower & medium voltage applications, the maximum operating voltage must be calculated. Given that a switch’s maximum standard commercial voltage is VSW ccv, when using the recommended multilayer inverter, the maximum operating voltage is equivalent to \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\raisebox{1ex}{\sqrt{1.5:}{\boldsymbol{V}}_{\boldsymbol{S}\boldsymbol{W}\boldsymbol{c}\boldsymbol{c}\boldsymbol{v}}}\!\left/\:\!\raisebox{-1ex}{\boldsymbol{\gamma:}}\right.$$\end{document} where γ is the switch’s safe operating factor, which is typically taken to be 1:7. Therefore, the maximum switch voltage may be used to establish the operation voltage of the proposed structure. When calculating the switch voltage for medium voltage applications, the maximum switch voltage of 3.3 kV is assumed to be the 3-phase operational RMS voltage of 2.3 kV. For 1-φ, the maximum voltage will be 1878 V, while the operational RMS voltage will be 1328 V. Therefore, with an RMS voltage of 1328 V, the voltage magnitudes of the 37-level MLI will be Va = Vb = Vc = 104.33 V, Vd = 730.33 V, and Ve = 834.66 V. Thus, Table V is used to determine the switch rated voltage for the suggested topology, and Table 6 is used to consider the VSW ccv. Table VII calculates and compares the costs of needed IGBTs and driver circuits for 1-φ proposed 37-level MLIs and existing 23-level, 13-level and 11-level MLIs^18,32,33^.

Since device costs fluctuate over time, the values in Table VII are indicative only. For fair comparison across topologies, normalized values such as cost per level (CF/L) are reported in Table VIII, which remain independent of market variations and allow a consistent evaluation of economic feasibility.

Table 6. The switches in the suggested topology’s voltage rating.SwitchesVoltageIGBTs RatingIGBT model numberStandardNormalS_1_313 V600 V600 V, 400 ACM20MD-12 HS_2_313 V600 V600 V, 400 AS_3_1565 V1700 V1700 V, 400 ACM400DU-34KAS_4_1565 V1700 V1700 V, 400 AS_5_1565 V1700 V1700 V, 400 AS_6_1565 V1700 V1700 V, 400 AS_7_313 V600 V600 V, 400 ACM20MD-12 HS_8_313 V600 V600 V, 400 AS_A_313 V600 V600 V, 400 AS_B_313 V600 V600 V, 400 AS_C_1565 V1700 V1700 V, 400 ACM400DU-34KAS_D_1565 V1700 V1700 V, 400 A

Comprehensive comparisons

With the assistance of the 37- level MLI that was constructed, Table 7 provides a description and analysis of the topologies that are now in place. Figure 10 (a) examines the number of levels, and Fig. 10 (b) examines the number of DC sources. Both of these comparisons are shown in the figure. A comparison of the total number of driver circuits is shown in Fig. 10(c), a comparison of the number of switches is shown in Fig. 10(d), a comparison of the respective levels of efficiency is shown in Fig. 10(e), and lastly, a comparison of the respective levels of cost function CF/L is shown in Fig. 10(f).

Fig. 10. Parameter-based comparisons of the proposed 37- level MLI.

In comparison with the 37-level inverter reported in^45^, the proposed topology achieves the same output levels with reduced device stress, lower TSV, and improved cost-per-level (CF/L). Moreover, hardware validation confirms higher efficiency and lower THD, highlighting the practical advantages of the proposed design over^45^.

Table 7. Cost comparison between the proposed topology and existing topologies.IGBT and Driver model numberVoltage and Current RatingUnit CostProposed ^34^

^33^

^18^ UnitsCostUnitsCostUnitsCostUnitsCostCM20MD-12 H600 V, 400 A$60.776$364.62----4$243.08CM400HA-24 A1200 V, 400 A$118--1$1186$7084$472CM400DU-34KA1700 V, 400 A$5166$30961$5166$3096--CM400DY-50 H2500 V, 400 A$550--1$550--4$2200CM400DY-66 H3300 V, 400 A$773--4$30922$1546--844-SD303C25S20C2500 V, 350 A$102.5--3$307.50----SKYPER-32PRO2Up to 1700 V$92.7112$1112.521$92.716$556.268$741.681SC0450V2A0-65Up to 6500 V$267.6--3$802.861$267.624$1070.48Overall cost$4573.14$5479.07$6173.88$4727.24Number of voltage output levels37111323Courtesy: www.nevonexpress.com, www.yaspro.com, * Prices may vary.

Table 8. Parameter-based comparisons of the proposed MLI.Topologies N SWI

N DCS

N LEV

N CAP

N DRK TSV(v)EfficiencyCF/Lα = 1.5α = 0.5 ^44^ 14431-148692.345.242.46 ^17^ 103312106792.64.031.87 ^45^ 1223141284NR3.042.64 ^13^ 12635-1263NR3.521.72 ^8^ 165352169287.811.810.2 ^37^ 12435-1252NR3.191.68 ^46^ 14537-149291.84.852.31Proposed12537-125593.263.181.62*NR = Metrics are not reported in the cited source.

Conclusion

In this study, an asymmetric 37-level MLI was proposed with the goal of lowering the price of MLIs, as well as their size and overall harmonic distortion. The MLI that has been recommended not only reduces the costs of maintenance but also achieves higher levels of efficiency and dependability. The 37- level inverter architecture that was presented is supported by the creation of the simulation model in MATLAB/Simulink as well as the validation using experimental outcomes. A comparison is made between the features and a wide variety of other complex topologies after the analysis has been completed. In comparison, the TSV voltage of MLI is 18V_DC_, the efficiency is 93.26%, the CF/L is 1.62 and 3.18 for = 0.5 and = 1.5, respectively, and the THD is 1.21%. The proposed inverter’s cost is far lower than it was in the more recent topologies. Multiple applications may be found for the proposed MLI structure that include active filters, Dynamic voltage restorers (DVRs), Electric Vehicles (EVs), Uninterruptible Power Supplies (UPS), and grid-connected Renewable Energy Systems (RES).