Closed-form design optimization for LLC converters with wide output voltage range based on FHA

TL;DR

This paper introduces a new, efficient method for designing LLC converters that work well across a wide range of voltages.

Contribution

A closed-form analytical design strategy is proposed, enabling optimal LLC converter design without numerical solvers.

Findings

The proposed method achieves full output voltage range under worst-case conditions.

The converter maintains soft switching across the entire operating range.

Peak efficiency is achieved near full load with reduced computational cost.

Abstract

This paper presents a novel design optimization strategy for LLC resonant converters that enhances full-load efficiency while operating across wide input and output voltage ranges. Achieving regulation over a wide output voltage range imposes more stringent design constraints on the converter, demanding higher inductance ratio and wider switching frequency range compared to constant output voltage applications. While numerical optimization techniques are effective for determining the optimal parameters of the converter; however, this effectiveness comes at a substantial computational cost. This work establishes a set of closed-form analytical equations that not only constitute a complete, step-by-step procedure for optimal design without reliance on numerical solvers, but also provide a framework for analyzing design trade-offs. The proposed methodology distinguishes itself from conventional approaches by offering a systematic and non-iterative procedure that is computationally efficient for determining an optimal design. The proposed procedure is validated through the simulation of a 495 W LLC converter specified for a wide operational range with a 320–370 V input and a 35–165 V output. The converter achieved the full output voltage range at the worst-case conditions and attained peak efficiency near the full load, while maintaining soft switching across the entire operating range.

Figures

Visualizing conditions (29), (30) and (31) at different values of α. The pink region is the original allowed space in Fig. [6](#Fig6) which would result in an invalid value for M_min_ (does not satisfy (27), the dark blue region is where 0 < M_min_ ≤ 1 (conditions (29) and (30)), the light blue region is where 1 < M_min_ < √2 (condition (31)). (a) α = 0.37, (b) α = 0.5, (c) α = 0.78, (d) α = 0.89.

Flowchart for the updated design procedure.

f_n, min_ and λ parameter space (Design Area) for the designed converter.

Semi-log graph (f_n_ in log scale) of the theoretical dc output voltage V_out_ versus the normalized switching frequency f_n_ of the designed converter.

Simulation Waveforms at No load and V_in, max_ = 370 V, (a) Mosfet Gate voltages for M1 V_GS, M1_ and M2 V_GS, M2_, (b) MOSFET M1 drain-source voltage V_DS, M1_ and drain-source current I_DS, M1_, (c) Resonant Tank input voltage V_DS, M2_ and input current I_Lr_, (d) Rectifier current for Diode D1 I_D1_ and Diode D2 I_D2_, (e) Diode D1 voltage V_D1_ and current I_D1_, (f) Load Voltage V_out_ and current I_RL_.

Simulation Waveforms at Full Load and V_in, min_ = 320 V, (a) Mosfet Gate voltages for M1 V_GS, M1_ and M2 V_GS, M2_, (*b*) MOSFET M1 drain-source voltage V_DS, M1_ and drain-source current I_DS, M1_, (c) Resonant Tank input voltage V_DS, M2_ and input current I_Lr_, (d) Rectifier current for Diode D1 I_D1_ and Diode D2 I_D2_, (e) Diode D1 voltage V_D1_ and current I_D1_, (f) Load Voltage V_out_ and current I_RL_.

Semi-Log graph for the lower bound on the minimum voltage gain M_min_, M_∞_ is the lowest possible voltage gain when Q = 0 and f_n_ > 1.

Efficiency η versus output power P_out_ at V_in, max_.

Flowchart for the initial design procedure.

LLC voltage gain M versus normalized switching frequency f_n_ under different values of Q.

LLC output voltage V_out_ versus normalized switching frequency f_n_ under different conditions. (a) V_in_ = 65 V, Q = 9 × 10^−3^ . (b) V_in_ = 60 V, Q = 0.755. (c) V_in_ = 60 V, Q = 1.27.

LLC waveforms, low side MOSFET drain source voltage V_DS, M2_, and resonant inductor current I_Lr_ (MOSFET current).

Contour map of the voltage gain M in terms of f_n, min_ and Q at a specific λ, the capacitive region is in pink while the inductive region is in green, Q_ZVS_ is the equation for the Q at the edge of ZVS (dark green), Q_ηmax_ is the equation for the Q that maximizes the efficiency (blue).

The design area (permissible region in f_n, min_ and λ parameter space), where ZVS and max efficiency at full load are achieved.

Semi-Log graph for the lower bound on the minimum voltage gain M_min_, M_∞_ is the lowest possible voltage gain when Q = 0 and f_n_ > 1.

Plot of f_n, max_ in terms of λ at different values of M_min_.

Flowchart for the initial design procedure.

Full text

Introduction

The LLC resonant converter has been widely used in DC–DC topologies for switched mode power supplies. In the literature, the LLC has been predominantly investigated in the context of constant output voltage applications^1–5^. Nevertheless, various authors have demonstrated that, by modulating the switching frequency, the LLC can manage wide-range output voltage regulation across large variations in both input voltage and load current^6–8^. Furthermore, the LLC can achieve robust soft switching under the worst-case conditions which is critical to minimizing electromagnetic interference (EMI) and maximizing efficiency. Switching the primary-side MOSFETs under zero-voltage switching (ZVS) eliminates reverse recovery losses, yielding lower total losses compared to zero-current switching (ZCS). Meanwhile, the rectifier diodes are switched under ZCS, further reducing losses^9^.

For constant output voltage applications, low inductance ratio and limited switching frequency range suffice; in contrast, wide output voltage applications necessitate simultaneously higher inductance ratio and broader frequency modulation, thereby further complicating the design optimization of the converter. Design procedures for employing the LLC as a variable voltage source with wide output voltage range have been proposed^10–13^. Furthermore, optimal design procedures for achieving the peak efficiency at a specified load for constant output voltage applications have been proposed^14,15^. Deriving closed form expressions for the component values is often unfeasible, given the high order nonlinear nature of the LLC circuit. Consequently, computer aided numerical optimization techniques have become prevalent for optimizing the converter^16^. There are several techniques commonly used to model the converter. The First Harmonic Approximation (FHA) method is widely employed to linearize the resonant network by retaining only its fundamental component, yielding an AC equivalent model, thereby significantly simplifying the analysis of the converter^17^.

Other approaches, like state-plane or time-domain analysis, are based on the exact modeling of the converter to provide precise description of the converter’s operation^18^. The exact models offer greater accuracy, nevertheless, at the expense of complicated equations which offer limited insights into the design tradeoffs and the influence of the converter parameters on the design constraints. In practice, the optimal design procedures employing the exact methods usually rely heavily on simulating the circuit with different component values^19,20^. Nevertheless, to avoid relying on simulators, methods based on numerical algorithms such as Stepwise Multi-Objective Parameter Optimization, and Surrogate Model have been proposed^21–23^. However, these methods require huge computational power and long execution time, thus limiting their utility.

In this paper, a novel optimal design procedure is introduced for the LLC resonant converter based on FHA. A step-by-step design procedure is proposed for optimizing this converter for wide output voltage range and improving efficiency at the full load while ensuring ZVS for the whole wide dynamic load range. The main advantage of the proposed methodology is that the converter design equations are derived analytically and expressed entirely in closed-form solutions, thus eliminating the need for the computationally expensive numerical methods used extensively in the predominant optimization methodologies proposed in literature. Furthermore, without requiring any auxiliary components to be added to the circuit, the proposed approach reduces cost, weight, and size while ensuring optimal performance.

In Sect. “LLC normalized DC output voltage”, the LLC resonant converter normalized dc output voltage based on the FHA approach is presented. The max and min voltage gain equations are stated in Sect. “Wide range operation necessary conditions”. An expression for approximating the conduction losses is presented in Sect. “Conduction losses approximation under the full-load condition”. The necessary equations for achieving wide-range operation and max efficiency while maintaining ZVS are derived in Sect. “The necessary conditions to achieve wide range and maximum efficiency simultaneously”. In Sect. “The proposed methodology derivation”, the equations governing the design procedure are derived. The design procedure independent parameters and the permissible parameter space are identified in Sect. “Identification of the independent parameters and the allowed parameter space”. The expressions for the dependent parameters in terms of the independent parameters are derived in Sect. “The converter dependent parameters in terms of the independent parameters”. In Sect. “The proposed updated design procedure”, the proposed design procedure and a step-by-step LLC converter parameters calculation are presented. The simulation results are discussed in Sect. “Simulation results”. Finally, the conclusions are listed in Sect. “Conclusion”.

LLC normalized DC output voltage

The LLC resonant converter topology, depicted in Fig. 1, employs a half-bridge arrangement in which any imbalance in gate-drive timing or other sources of asymmetry produces a DC offset in the transformer’s primary current, risking core saturation. By inserting the resonant capacitor Cr, this DC component is blocked, both preventing core saturation and forming the essential resonant network that governs the converter behavior. In this topology, the transformer’s turns ratio is n = Np/Ns, where Np and Ns denote the primary and secondary winding counts, respectively. The inductances Lm and Lr represent the magnetizing inductance and the primary-referred leakage inductance, respectively.

Fig. 1(a) LLC circuit topology, (b) LLC ac equivalent circuit.

By employing the FHA method, the nonlinear circuit presented in Fig. 1a can be approximated by the linear circuit shown in Fig. 1b, where the combined effect of the rectifier and the load are represented by:

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{R}_{o}=\frac{8}{{\pi\:}^{2}}{R}_{L}$$\end{document}

where RL is the load resistance^24^. Furthermore, the following parameters are also defined:

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\lambda\:=\frac{{L}_{r}}{{L}_{m}}\:,\:{f}_{n}=\frac{{f}_{s}}{{f}_{r}}\:,\:Q=\frac{\sqrt{{L}_{r}/{C}_{r}}}{{n}^{2}{R}_{o}}\:,{f}_{r}=\frac{1}{2\pi\:\sqrt{{L}_{r}{C}_{r}}}\:,\text{}{f}_{\text{n,min}}=\:\frac{{f}_{\text{s,min}}}{{f}_{r}},{f}_{\text{n,max}}=\:\frac{{f}_{\text{s,max}}}{{f}_{r}}$$\end{document}

where λ is the inductance ratio, fn is the normalized switching frequency, fs is the switching frequency, fr is the resonant frequency, Q is the quality factor, fn,min is the normalized minimum frequency, fs,min is the minimum switching frequency, fn,max is the normalized maximum frequency, and fs,max is the maximum switching frequency. The voltage gain magnitude can be expressed^24^

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:M=\frac{2\:n\:{V}_{out}}{{V}_{in}}=\frac{1}{\sqrt{{(1+\lambda\:-\:\lambda\:/{{f}_{n}}^{2}\:)}^{2}+{\left(Q{f}_{n}\right(1-1/{{f}_{n}}^{2}\left)\right)}^{2}}}$$\end{document}

where Vout is the output voltage, Vin is the input voltage, and M is the magnitude of the voltage gain of the converter. Figure 2 depicts the converter’s voltage gain characteristics (3) under various values of Q. The figure demonstrates the distinct operating regions of the converter. Zero-voltage switching (ZVS) is achievable wherever the gain curve slopes downward. Unlike a series resonant converter, which attains ZVS only above its resonant frequency, the LLC configuration can achieve ZVS both below and above resonant frequency. However, operating above the resonant frequency exhibits the same drawbacks as the series converter, such as requiring a wide frequency range for voltage regulation. The optimal operating frequency is at resonance, where switching losses and circulating currents are minimal. In practice, variations in the input voltage and load typically necessitate adjusting the operating frequency above or below the resonant frequency.

Fig. 2LLC voltage gain M versus normalized switching frequency f_n_ under different values of Q.

The following sections will present the proposed methodology for LLC converter design. Table 1 summarizes the comparison between the proposed methodology and the other methodologies in the literature.

Table 1. Qualitative comparison between different optimal design methodologies.Comparison pointProposed ^10^

^15^

^19^

^21–23^

^25^

^26^

^27^ Supports wide range output voltage operationYesYesNoYesYesNoYesYesSupports wide range input voltage operationYesYesYesNoYesYesYesNoOptimizes the efficiencyYesNoYesYesYesYesYesYesRequires multiple iterationsNoYesNoYesYesYesNoNoBased on numerical optimizationNoNoNoNoYesNoNoNoBased on closed form expressionsYesYesYesYesNoYesYesYesBased on FHA/TDA (time domain analysis)FHAFHAFHATDATDATDATDAFHAComputation time requiredLowLowLowMidHighMidMidLowDesign methodology ease of useEasyMidEasyMidHardMidMidEasy

Based on the comparison presented in Table 1, the proposed method demonstrates several key advantages over existing approaches:

• Supporting wide voltage range operation for both input and output^15,19,25,27^.
• Avoiding the need for multiple iterations^10^ and for solving a large set of equations numerically^26^.
• Eliminating reliance on computationally intensive numerical optimization^21–23^.

The main limitation of the proposed approach compared to other published methods is its reliance on FHA and not the more accurate TDA.

Wide range operation necessary conditions

In this section, the necessary conditions for achieving the wide range operation are derived. From (3), the relationship between the dc output voltage of the converter and the normalized switching frequency fn has been depicted in Fig. 3 for various values of the quality factor (Q) and different input and output voltage conditions^7^. In this figure, curve (a) represents the converter operating under no-load with the input voltage at its maximum. However, curve (b) corresponds to the scenario where the converter is supplied with the minimum input voltage under the full-load condition. While curve (c) depicts the scenario of minimum input voltage together with maximum load current. Accordingly, segment A-B is the switching frequency range for regulating the output voltage at its maximum value, while the C-D interval is for regulating the output voltage at its minimum value.

Fig. 3LLC output voltage V_out_ versus normalized switching frequency f_n_ under different conditions. (a) V_in_ = 65 V, Q = 9 × 10^−3^ . (b) V_in_ = 60 V, Q = 0.755. (c) V_in_ = 60 V, Q = 1.27.

More specifically, point A represents operating at the minimum Vin and the maximum Vout at the full load condition, while point B represents operating at the maximum Vin and the maximum Vout at no load. Moreover, point C represents operating at the minimum Vin and the minimum Vout while drawing the max load current. Finally, point D represents operating at the maximum Vin and the minimum Vout at no load. From Fig. 3, the operating points of the converter for all variations in Vin, Vout and load current are located between points A and D. Consequently, achieving points A and D automatically guarantees achieving the other points over the entire operating range of the converter. Thus, the necessary constraints for the wide range operation are achieving the maximum voltage gain (Mmax) at point A and the minimum voltage gain (Mmin) at point D.

The maximum voltage gain occurs when the minimum input voltage Vin, min is applied to the converter and the maximum output voltage Vout, max is requested under the full-load condition. From (3), the maximum voltage gain can be expressed as

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{max}=\:\frac{2\:n\:{V}_{out,max}}{{V}_{in,min}}\:=\frac{1}{\sqrt{{(1+\lambda\:-\:\lambda\:/{{f}_{n,min}}^{2}\:)}^{2}+{\left({Q}_{FL}\right(1-1/{{f}_{n,min}}^{2}\left)\right)}^{2}}}$$\end{document}

The permissible input voltage range for realizing the maximum output voltage is determined by the converter’s peak voltage gain. Consequently, the converter’s gain curve must exhibit a sufficiently high peak to accommodate the full range of expected input voltages. Furthermore, the ZVS is lost when operating at a frequency below that of the peak gain point^19^, the capacitive region as illustrated in Fig. 2. To ensure robust ZVS operation during transient conditions, a safety margin is necessary when specifying the maximum gain. In practice, it is common to allocate a 10–20% safety margin above the required maximum gain (4), thus guarantying reliable ZVS. Additionally, under light-load or no-load conditions (where Q approaches zero), the converter must be capable of achieving the minimum output voltage Vout, min even when the maximum input voltage Vin, max is applied. From (3), the minimum voltage gain can be expressed as

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{min}=\:\frac{2\:n\:{V}_{out,min}}{{V}_{in,max}}\:=1/(1+\lambda\:-\lambda\:/{{f}_{n,max}}^{2})$$\end{document}

Conduction losses approximation under the full-load condition

To ensure high efficiency, the converter must be designed in such a way as to achieve max efficiency near the full-load operating point, since this is the most probable operating point over the converter’s lifetime. To estimate the converter’s efficiency, an approximate expression for the conduction losses of the converter was derived^10^. The approximate expression is based on the following assumptions:

• The current drawn by the MOSFETs during the on-state is approximated with its first harmonic as shown in Fig. 4.
• The overall resistance seen by that current is lumped into a single equivalent resistance.
• The average power dissipation is evaluated by integrating the product of this equivalent resistance and the square of the approximated sinusoidal current over one switching period.
• The maximum value for the conduction losses is realized at Point A in Fig. 3 (more specifically at Vout, max, Vin, min, fn, min, and QFL).

Fig. 4LLC waveforms, low side MOSFET drain source voltage V_DS, M2_, and resonant inductor current I_Lr_ (MOSFET current).

The approximate expression for the normalized peak conduction losses

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{P}_{loss}=\frac{{P}_{cond,max}}{{r}_{DS}{V}_{in,norm}^{2}\:\left({L}_{r}/{C}_{r}\right)}=\frac{1}{{\pi\:}^{2}}\frac{{({\lambda\:}^{2}+{Q}_{FL\:}^{2}{f}_{n,min}^{2})}^{2}}{{Q}_{FL\:}^{2}{f}_{n,min}^{4}}{(V}_{in,min}^{2}/{V}_{in,norm}^{2})\:\:$$\end{document}

Where \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{V}_{in,norm}=\:({V}_{in,min}+{V}_{in,max})/2$$\end{document} .

The necessary conditions to achieve wide range and maximum efficiency simultaneously

In this section, the necessary conditions that must be satisfied by the converter to achieve output voltage wide range operation, attain max efficiency near the full-load condition, and ensure ZVS across the entire operating range are derived.

Conditions for operating in the inductive region

Since \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:0\le\:Q\le\:{Q}_{FL}$$\end{document} for all permissible values of Q, where Q achieves 0 at no-load and QFL at full-load. From^24^, a sufficient condition for the converter to be operating inside the ZVS region for all permissible Q,

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{Q}_{FL}\le\:\sqrt{\frac{\lambda\:}{1-{f}_{n,min}^{2}}-\frac{{\lambda\:}^{2}}{{f}_{n,min}^{2}}}$$\end{document}

Where equality holds when operating at the edge of the ZVS region since the boundary between the ZVS and ZCS region is part of the ZVS region. To ensure that (7) yields non-negative real value for QFL, the following conditions must be satisfied

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:0<\lambda\:\le\:\frac{{f}_{n,min}^{2}}{1-{f}_{n,min}^{2}}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:0<{f}_{n,min}<1\:$$\end{document}

Achieving maximum efficiency at the full-load condition

To place the peak of the converter’s efficiency at the full-load operating point (point A in Fig. 3), the efficiency can be expressed at any load in terms of Q as

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\eta\:\left(Q\right)=\frac{{P}_{out}\left(Q\right)}{{P}_{out}\left(Q\right)+{P}_{loss}\left(Q\right)}$$\end{document}

Assuming that the output power is constant and equal to the full load power (10), can be rewritten as

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\eta\:\left({Q}_{FL}\right)=\frac{{P}_{out,FL}}{{P}_{out,FL}+{P}_{loss}\left({Q}_{FL}\right)}$$\end{document}

Maximizing the efficiency becomes equivalent to minimizing the power losses

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{max}\left[\eta\:\right({Q}_{{FL}}\left)\right]\equiv\:{min}\left[{P}_{loss}\right({Q}_{FL}\left)\right]\equiv\:\:\:\:\frac{\partial\:{P}_{loss}\left({Q}_{FL},{f}_{n,min},\lambda\:\right)}{\partial\:{Q}_{FL}}=0$$\end{document}

Differentiating (6) with respect to QFL results in,

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{Q }_{FL}=\frac{\lambda\:}{{f}_{n,min}}$$\end{document}

Differentiating (6) with respect to QFL twice and applying (13) then simplifying

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\frac{{{\partial\:}^{2}P}_{loss}\left({Q}_{FL},{f}_{n,min},\lambda\:\right)}{{\partial\:{Q}_{FL}}^{2}}=\:\frac{8\:{(V}_{in,min}^{2}/{V}_{in,norm}^{2})\:\:}{{\pi\:}^{2}}>0$$\end{document}

The second derivative test in (14) proves that (13) minimizes the power loss, thus maximizing the efficiency.

To visualize (13), Fig. 5 plots the contour maps of the voltage gain M at a specific λ with fn, min on the x-axis and Q on the y-axis. The graph is split into two regions, the inductive region where the ZVS condition (7) is satisfied, while the capacitive region where the ZVS condition is not satisfied (ZCS is satisfied instead). The QZVS curve separates the two regions, and it is part of the inductive region, according to (7). The Qηmax curve is the locus of all points where the efficiency is maximum (13). From this figure, to maximize the efficiency at the full load condition and achieve ZVS, the converter must be designed such that point A, in Fig. 3, is placed at the intersection of the Qηmax curve and the inductive region as shown in Fig. 5.

Fig. 5. Contour map of the voltage gain M in terms of f_n, min_ and Q at a specific λ, the capacitive region is in pink while the inductive region is in green, Q_ZVS_ is the equation for the Q at the edge of ZVS (dark green), Q_ηmax_ is the equation for the Q that maximizes the efficiency (blue).

The proposed methodology derivation

Identification of the independent parameters and the allowed parameter space

Substituting the max efficiency QFL from (13) into ZVS region inequality (7)

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\frac{\lambda\:}{{f}_{n,min}}\le\:\sqrt{\frac{\lambda\:}{1-{f}_{n,min}^{2}}-\frac{{\lambda\:}^{2}}{{f}_{n,min}^{2}}}$$\end{document}

Simplifying (15), gives the following inequalities

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:0<\lambda\:\le\:\frac{{f}_{n,min}^{2}}{2-2{f}_{n,min}^{2}}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:0<{f}_{n,min}<1\:\:$$\end{document}

Equation (15) is equivalent to (16) if and only if (17) is satisfied. To ensure that the derivation is mathematically sound, the inequalities (16 and 17) must satisfy the validity conditions (8, 9). To prove this, it can be observed that (9 and 17) are identical, and through some straightforward algebraic manipulations it can be shown that the region defined by (16 and 17) is situated entirely within the boundaries of the region defined by (8). Therefore (16 and 17), satisfy (8 and 9).

Equations (16 and 17) are necessary conditions to ensure achieving wide range operation, while maintaining ZVS across the whole operation, and attaining the max efficiency at the full load. Therefore, to ensure that the converter achieves these conditions, fn, min and λ must be chosen in such a way as to satisfy the conditions (16 and 17). This result is visualized in Fig. 6. Within the parameter space spanning all combinations of fn, min and λ representing the different possible designs of the converter, (16) and (17) establish a region of permissible values, effectively restricting the permissible parameter combinations that can be used to design the converter (the design area).

Fig. 6. The design area (permissible region in f_n, min_ and λ parameter space), where ZVS and max efficiency at full load are achieved.

This can be interpreted as follows, the objectives of achieving wide range operation, maintaining ZVS for the entire operating range, and attaining max efficiency at the full load effectively restricting all of the converter’s degrees of freedom except for two. In other words, fn, min and λ are the only independent parameters of the converter while the rest of the converter’s parameters can be expressed in terms of fn, min and λ. Although fn, min and λ are independent design parameters, their permissible values are not entirely independent. In fact, a dependency exists between the two where the selection of one parameter’s value restricts the feasible range of the other as can be seen in Fig. 6. The next step in the design procedure is to express each parameter of the converter in terms of fn, min and λ.

The converter dependent parameters in terms of the independent parameters

The maximum voltage gain

To express the max voltage gain Mmax in terms of fn, min and λ, substituting in the voltage gain Eq. (4) using the QFL at max efficiency (13),

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{max}=\frac{{f}_{n,min}^{2}}{\sqrt{{f}_{n,min}^{4}+2{f}_{n,min}^{2}(-1+{f}_{n,min}^{2})\lambda\:+2{(-1+{f}_{n,min}^{2})}^{2}{\lambda\:}^{2}}}$$\end{document}

It can be shown that for the entire range defined by (17) for fn, min and (16) for λ (18), is positive real. Therefore, there are no additional validity conditions. Moreover, combining the constraints of fn, min (17) and λ (16) with (18), then simplifying gives:

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:1<{M}_{max}\le\:\sqrt{2}$$\end{document}

This is the range of the permissible values for Mmax. The conditions under which the lower and upper bounds are attained are derived next. The Lower bound in (19) is achieved when the voltage gain of the converter approaches unity which happens as fn, min approaches 1 regardless of the value of λ. The upper bound in (19) is achieved when the gain is maximized while remaining in the ZVS region, this happens along the edge of the ZVS region. To prove this, substituting the expression for the QFL at max efficiency (13) into the expression for the QFL at the edge of the ZVS region (7) when the equality holds), then simplifying gives

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\lambda\:=\frac{{f}_{n,min}^{2}}{2-2{f}_{n,min}^{2}}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:0<{f}_{n,min}<1\:\:$$\end{document}

Deriving Eq. (19) again but this time using (20) instead of (16) results in

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{max}=\sqrt{2}$$\end{document}

Equation (22) shows that the upper bound in (19) is attained when the converter maximum voltage gain point is placed at the edge of the ZVS region while also achieving maximum efficiency at full load. In other words, when point A in Fig. 3 is placed at the intersection of the Qηmax curve and the QZVS curve in Fig. 5.

Accordingly, to increase the maximum voltage gain of the converter Mmax, the converter maximum voltage gain point (point A in Fig. 3) must be placed closer to the edge of the ZVS region (the Q_ZVS_ curve in Fig. 5). To achieve this, λ must be chosen in (16) to be closer to its upper bound. In summary, the designer can increase the maximum voltage gain of the converter by choosing fn, min and λ closer to the left boundary of the allowed region in Fig. 6.

The transformer’s turns ratio

To express the transformer’s turns ratio n in terms of fn, min and λ, solving (4) for n,

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:n=\:\frac{{M}_{max}\:{V}_{in,min}}{2\:\:{V}_{out,max}}$$\end{document}

To express the minimum voltage gain Mmin in terms of fn, min and λ, substituting (23) into (5),

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{min}={M}_{max}\:\frac{{V}_{in,min}{\:V}_{out,min}}{{V}_{in,max}{\:V}_{out,max}}\:=\:{M}_{max}\:\alpha\:$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\alpha\:=\frac{{V}_{in,min}{\:V}_{out,min}}{{V}_{in,max}{\:V}_{out,max}}=\frac{{V}_{in,min}}{{V}_{in,max}}\times\:\frac{{\:V}_{out,min}}{{\:V}_{out,max}}$$\end{document}

The expression for Mmin in (24) can be written in terms of fn, min and λ by substituting for Mmax using (18). The ratio of voltages in (24) will play an important role in the design procedure. Therefore, it is introduced in (25) as the “voltage ratio product” and given the symbol “α”. The voltage ratio product α is defined as the product of two voltage ratios, the ratio of the input voltage range and the ratio of the output voltage range. If the converter is acting as a constant voltage source and operates only at a specific input voltage, then α will equal one. However, if the converter is operating as a wide range voltage source with variable input voltage, then α will have a value between zero and one. Furthermore, α will get closer to zero as the operating voltage ranges of the converter become wider. Therefore, α can be interpreted as a measure of the converter’s wide range operation, the wider the operating voltage the smaller α becomes.

Consequently, as α becomes smaller the converter design becomes harder, because demanding wider voltage ranges from the converter will effectively reduce the number of admissible converter designs. It will be shown later that this will impose more restrictive constraints on the parameters of the converter which in turn means that the allowed region in the parameter space will be smaller.

From the definition of α and the realistic values of the input and output voltages, the range of α is restricted to be: \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:0<{\upalpha\:}<1$$\end{document} . This interval can be derived from the facts that \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{\upalpha\:}\:=\:1$$\end{document} can only happen if the corresponding input and output voltages are equal, while \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{\upalpha\:}\:=\:0$$\end{document} can only happen if the minimum or the maximum of input voltage is zero.

The maximum normalized frequency

To express the maximum normalized frequency fn, max in terms of fn, min and λ, solving (25) for fn, max,

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{f}_{n,max}=\sqrt{\frac{{M}_{min}\lambda\:}{-1+{M}_{min}+{M}_{min}\lambda\:}}$$\end{document}

To rewrite (26) to be in terms of fn, min and λ only, substitute (18) into (24) then into (26).

To obtain positive real value for fn, max from (26), the radicand must be positive real. After some algebraic manipulations, the following validity conditions are derived,

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:(0<{M}_{min}\le\:1\:\&\:\lambda\:>\frac{1-{M}_{min}}{{M}_{min}})\:\:OR\:\:(1<{M}_{min}<\sqrt{2}\:\&\:\lambda\:>0)$$\end{document}

The conditions in (27) are additional constraints that must be satisfied, however they are not satisfied automatically if (16, 17) are satisfied. Therefore, these additional necessary conditions will now be analyzed in detail.

There are two ways to satisfy (27) either satisfy the first condition or the second condition. The first condition in (27) states that there is an additional constraint on Mmin and λ when Mmin is less than 1. From the voltage gain equation, it can be deduced that the gain is less than 1 only when the normalized frequency is higher than 1. Rearranging the first condition,

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{min}>\frac{1}{1+\lambda\:}$$\end{document}

The inequality (28) is recognized as the well know expression for maximum voltage gain available when the fn > 1^24^. This can be seen clearly in Fig. 7.

Fig. 7. Semi-Log graph for the lower bound on the minimum voltage gain M_min_, M_∞_ is the lowest possible voltage gain when Q = 0 and f_n_ > 1.

The first condition in (27) can be interpreted as follows, after fn, min and λ are chosen in the allowed region in Fig. 6, Mmin is calculated from (24), and if Mmin < 1 then condition (28) must be checked. If condition (28) is respected by the chosen fn, min and λ then we can proceed with the next step in the design. Otherwise, the choice is invalid and another combination of fn, min and λ must be chosen. This process must be repeated until a valid combination is reached, later we will show another procedure which does not require any repetitions. The first condition can be summarized as follows, if Mmin < 1 then condition (28) will restrict the allowed region in the parameter space in Fig. 6. Consequently, condition (28) can be regarded as an indirect constraint on fn, min and λ.

The second condition in (27) states that if Mmin is larger than 1 then there are no additional constraints imposed. Collectively (27), states that if the minimum voltage gain Mmin (point D in Fig. 3) is higher than 1 then the entire allowed region in Fig. 6 is indeed allowed. However, if Mmin is less than or equal to 1 then there is an additional constraint which will effectively reduce the allowed region in Fig. 6.

To get a better understanding of (26 and 27), Eq. (26) is plotted in Fig. 8, where the asymptotes are defined by the equation \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\lambda\:=\frac{1-{M}_{min}}{{M}_{min}}$$\end{document} . Hence, for the cases where Mmin < 1, as λ approaches \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\frac{1-{M}_{min}}{{M}_{min}}$$\end{document} the fn, max approaches infinity. While for the cases where Mmin > 1, λ can take any value and fn, max will always be between 0 and 1.

Fig. 8. Plot of f_n, max_ in terms of λ at different values of M_min_.

In the previous sections, expressions for each of the converter’s parameters in terms of fn, min and λ have been derived. The design procedure is summarized in the flowchart of Fig. 9. Clearly, this flowchart is iterative, since choosing any combination of fn, min and λ inside the allowed region in Fig. 6 does not always guarantee that the condition (27) is satisfied. To overcome this limitation, in the next section Fig. 6 will be updated in such a way as to incorporate the condition (27) into the allowed region of fn, min and λ, to guarantee that the chosen fn, min and λ will always satisfy the condition (27). Later, a new flowchart will be presented for the updated design procedure.

Fig. 9. Flowchart for the initial design procedure.

Incorporating the additional constraints into the allowed parameter space

The first step is to rewrite the conditions (27) in terms of fn, min and λ. Substituting (18) into (24) then into (27), then simplifying considering (16, 17),

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:IF\:(\:\begin{array}{cc}0<{M}_{min}\le\:1\:\:\&\:0<\alpha\:\le\:\frac{1}{\sqrt{2}}\:)&\:\end{array}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\frac{{f}_{n,min}^{2}(-1-{f}_{n,min}^{2}(-1+{\alpha\:}^{2})+\sqrt{-1+2{\alpha\:}^{2}+{f}_{n,min}^{2}(-2+{f}_{n,min}^{2})(-1+{\alpha\:}^{2})})}{-2+4{f}_{n,min}^{2}+{f}_{n,min}^{4}(-2+{\alpha\:}^{2})}<\lambda\:\le\:\frac{{f}_{n,min}^{2}}{2-2{f}_{n,min}^{2}}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:IF\:(\:\begin{array}{cc}0<{M}_{min}\le\:1\:\:\&\:\frac{1}{\sqrt{2}}<\alpha\:<1\:)&\:\end{array}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\frac{{f}_{n,min}^{2}(-1-{f}_{n,min}^{2}(-1+{\alpha\:}^{2})+\sqrt{-1+2{\alpha\:}^{2}+{f}_{n,min}^{2}(-2+{f}_{n,min}^{2})(-1+{\alpha\:}^{2})})}{-2+4{f}_{n,min}^{2}+{f}_{n,min}^{4}(-2+{\alpha\:}^{2})}<\lambda\:\le\:\frac{{f}_{n,min}^{2}(-1+\sqrt{-1+2{\alpha\:}^{2}})}{2(-1+{f}_{n,min}^{2})}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:IF\:(\:\begin{array}{cc}1<{M}_{min}<\sqrt{2}\:\:\&\:\frac{1}{\sqrt{2}}<\alpha\:<1\:)&\:\end{array}$$\end{document} \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\frac{{f}_{n,min}^{2}(-1+\sqrt{-1+2{\alpha\:}^{2}})}{2(-1+{f}_{n,min}^{2})}<\lambda\:\le\:\frac{{f}_{n,min}^{2}}{2-2{f}_{n,min}^{2}}$$\end{document}

Conditions (29), (30) and (31) are equivalent to (27). These conditions can be summarized as follows:

If \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\alpha\:\le\:\frac{1}{\sqrt{2}}$$\end{document} then \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{min}\le\:1$$\end{document} and this will restrict the allowed space in Fig. 6 (allowed fn, min and λ) as per the condition (29). If \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\alpha\:>\frac{1}{\sqrt{2}}$$\end{document} then either \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{min}\le\:1$$\end{document} or \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{min}>1$$\end{document} depending on λ and fn, min, if \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\lambda\:\le\:\frac{{f}_{n,min}^{2}(-1+\sqrt{-1+2{\alpha\:}^{2}})}{2(-1+{f}_{n,min}^{2})}$$\end{document} then \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{min}\le\:1$$\end{document} and the condition (30) applies otherwise \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{M}_{min}>1$$\end{document} and the condition (31) applies.

Since Mmin is not known at the beginning of the design process, it is crucial to rewrite the antecedent conditions inside the “If ” parenthesis in the conditional expressions (29), (30) and (31) to be in terms of λ and fn, min instead. Accordingly, (29), (30) and (31) can be rewritten as:

• \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:IF\begin{array}{cc}(0<\alpha\:\le\:\frac{1}{\sqrt{2}}\:)&\:Then,\:\end{array}\:\:\:0<{M}_{min}\le\:1$$\end{document} and the condition (29) is applicable.
• \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:IF\begin{array}{cc}(\frac{1}{\sqrt{2}}<\alpha\:<1\:\&\:\:\lambda\:\le\:\frac{{f}_{n,min}^{2}\left(-1+\sqrt{-1+2{\alpha\:}^{2}}\right)}{2\left(-1+{f}_{n,min}^{2}\right)}\:)&\:Then,\end{array}\:\:\:0<{M}_{min}\le\:1$$\end{document} and the condition (30) is applicable.
• \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:IF\begin{array}{cc} \begin{array}{cc}(\frac{1}{\sqrt{2}}<\alpha\:<1\:\&\:\lambda\:>\frac{{f}_{n,min}^{2}(-1+\sqrt{-1+2{\alpha\:}^{2}})}{2(-1+{f}_{n,min}^{2})}\:)&\:Then,\:\end{array}&\:1<{M}_{min}<\sqrt{2}\end{array}$$\end{document} and the condition (31) is applicable.

In summary, as α decreases, which indicates that wider operating voltage range is required, the smaller the allowed region in Fig. 6 becomes since more restriction are imposed on the allowed fn, min and λ combinations. In Fig. 10, conditions (29), (30) and (31) are plotted for different values of α to visualize how fn, min and λ allowed space in Fig. 6 changes as α changes.

Fig. 10. Visualizing conditions (29), (30) and (31) at different values of α. The pink region is the original allowed space in Fig. 6 which would result in an invalid value for M_min_ (does not satisfy (27), the dark blue region is where 0 < M_min_ ≤ 1 (conditions (29) and (30)), the light blue region is where 1 < M_min_ < √2 (condition (31)). (a) α = 0.37, (b) α = 0.5, (c) α = 0.78, (d) α = 0.89.

As α starts very small in Fig. 10a, condition (29) severely restricts the allowed space, the value of the minimum voltage gain Mmin can never exceed one. As α increases in Fig. 10b, the restriction imposed by the condition (29) is relaxed, thus enlarging the allowing space, while Mmin is still restricted to not exceed one. In Fig. 10c, α is increased above the value of \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:1/\sqrt{2}$$\end{document} , the allowed space is further enlarged. Moreover, the allowed space now consists of two regions with different properties, one region is where \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:0<{M}_{min}\le\:1$$\end{document} as per the condition (30) while the other region is where \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:1<{M}_{min}<\sqrt{2}$$\end{document} as per the condition (31). In Fig. 10d, α is increased even further, the allowed space is further enlarged while maintaining the two distinct regions that first appeared in Fig. 10c.

Design equations for the LLC circuit elements

From the equations for λ (16), QFL (13), fn, max (26), and (2), the LLC circuit parameters can be calculated

\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{L}_{r}=\frac{4{f}_{n,max}{n}^{2}{Q}_{FL}{R}_{L}}{{f}_{s,max}{\pi\:}^{3}},\:\:{c}_{r}=\frac{{f}_{n,max}\pi\:}{16{f}_{s,max}{n}^{2}{Q}_{FL}{R}_{L}},\:\:{L}_{m}=\frac{4{f}_{n,max}{n}^{2}{Q}_{FL}{R}_{L}}{{f}_{s,max}{\pi\:}^{3}\lambda\:}$$\end{document}

The proposed algorithm will optimize the efficiency of the converter in such a way that the peak efficiency will occur at a load resistance near the value of RL. Therefore, it is common to choose this resistance value to be the most common load of the converter during operation^15^ which usually is the full-load condition, thereby RL can be calculated from \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{R}_{L}=\:{V}_{out,max}/{I}_{out,max}$$\end{document} ^10^.

The proposed updated design procedure

In this section the updated design procedure is summarized in the flowchart of Fig. 11 and then applied to design the LLC converter. As can be seen in the flowchart, there are no loops or conditions to check, the design procedure is straightforward. Any combination of fn, min and λ that satisfy the conditions (29), (30) and (31) are guaranteed to produce a valid design. As long as \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:0<\alpha<1$$\end{document} is satisfied, the proposed algorithm will always generate a valid optimal design, however, if the input or output ranges are very wide then the generated design could be impractical for implementation.

Fig. 11. Flowchart for the updated design procedure.

The converter designed in this section shall meet the following specifications: the minimum input voltage Vin, min = 320 V, the maximum input voltage Vin, max = 370 V, the maximum switching frequency fs, max = 315 kHz, the maximum load current Iout, max = 3.0 A, the minimum output voltage Vout, min = 35 V, the maximum output voltage Vout, max = 165 V, the full-load Resistance RL = 165 V / 3.0 A = 55 Ω. Following the design procedure flowchart Fig. 11,

Step 0: Update the maximum output voltage Vout, max to incorporate a 10% safety factor. Vout, max = 181.5 V.

Step 1: Calculate α, from (25), α = 0.166778.

Step 2: To plot the fn, min and λ allowed space, it must be determined which of the conditions (29), (30) and (31) is applicable. Considering the value of α calculated in step 1, (29) is the applicable condition. The fn, min and λ parameter space is plotted in Fig. 12.

Fig. 12f_n, min_ and λ parameter space (Design Area) for the designed converter.

Step 3: Choose fn, min and λ within the allowed space in Fig. 12. the entire region \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:0<{M}_{min}\le\:1$$\end{document} in Fig. 12 is valid in the sense that any point chosen there would lead to a converter that can achieve all of the specifications. As can be seen in Fig. 12, the combination (fn, min = 0.94 and λ = 3.5) is chosen within the allowed space.

Step 4: Calculate the converter parameters, QFL = 3.72 from (13), Mmax = 1.41 from (18), n = 1.243 from (23), Mmin = 0.235 from (24), fn, max = 3.76 from (26).

Step 5: Calculate the converter LLC values, Lr = 487.4 µH, Cr = 7.4 nF, Lm = 139.2 µH from (32).

It is clearly evident that the proposed design procedure is straight forward and does not require any iterations.

It is preferable to design the converter with small frequency variation range and compact components. From (32), it can be shown that increasing fs, max and decreasing fn, max will decrease the size of the components. Moreover, based on Fig. 8, Eqs. (26) and (27), to decrease fn, max, λ must be increased to be much higher than \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:\frac{1-{M}_{min}}{{M}_{min}}$$\end{document} . However, based on (2), increasing λ will increase the size of Lr. Therefore, there is a tradeoff between decreasing the size of the components (Lr, Lm, and Cr) and decreasing the frequency variation range ( \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\:{f}_{n,max}-\:{f}_{n,min}$$\end{document} ). Nevertheless, using the closed form equations derived in this paper, the designer can control the design tradeoffs while ensuring that the design will meet the specifications.

Smaller values of fn, max are usually preferred to reduce the frequency variation range. In that case, the proposed methodology gives quite accurate results. However, for large values of fn, max, the accuracy of this procedure is reduced due to the influence of higher-order harmonics that are neglected in the FHA approach, which is an inherent limitation for all design procedures based on the FHA. Nevertheless, the design procedure remains valid and gives acceptable results. Therefore, in applications where large values of fn, max is unavoidable, it is recommended to validate this analytical approach with simulations.

Smaller values of λ are usually preferred to allow the physical integration of the Lr and Lm into a single transformer. However, the value of λ in this case study is large, thus it is not possible to physically integrate the Lr and Lm. This limitation is a direct consequence of requiring the converter to operate with wide voltage range in both the input (320–370 V) and output (35–165 V). In other words, the wider the voltage ranges, the higher λ becomes. This is a known limitation of wide voltage range design techniques, for example^10^.

Simulation results

To validate the proposed design strategy, presented in Sect. “The proposed updated design procedure”, the designed LLC converter has been simulated at a steady state under different scenarios using LTSPICE. The parameters and specifications of the designed LLC resonant converter have been tabulated in Table 2.

Table 2. Key parameters of the designed Converter.ParameterSymbolValueLoss model used in simulationInput VoltageVin, min – Vin, max320–370 V–Output VoltageVout, min – Vout, max35–165 V–Output Current I out, max 3 A (at full load)–Output Power P out, max 495 W (Vout, max x Iout, max)–Power MOSFETsM₁, M₂2×STP12NM50Shichman-Hodges model (SPICE VDMOS Level 1 model)With R_ds, on_ = 300mΩ at I_DS_= 5.8 APower diodesD₁ – D₄4×STTH802Shockley diode model with parasitic (SPICE D model)With V_total drop_=922mV at I_D_=5.2 AInductance-ratio λ 3.5–Transformer turns ratio n 1.243–Resonant capacitance Cr 7.4 nFAssume constant ESR = 50 mΩMagnetizing inductance Lm 139.2 µHAssume constant ESR = 150 mΩResonant inductance Lr 487.4 µHAssume constant ESR = 200 mΩDead-time ΔT 350 ns–

Figure 13 shows the output voltage transfer function of the designed converter versus the normalized switching frequency under the two worst-case scenarios. The first scenario is operating at the full-load condition with minimum input voltage, curve (b) in Fig. 13. This scenario represents point A in Fig. 3 when operating at fn, min. The peak voltage is equal to 181.5 V, achieved at fn = 0.94, which is 10% higher than the output voltage required of 165 V, achieved at fn, min = 0.96. The second scenario is operating under the no-load condition with maximum input voltage, curve (a) in Fig. 13, which represents point D in Fig. 3, where the output voltage is 35 V at fn, max = 3.76. This demonstrates that the converter succeeded in achieving the full operating voltage ranges as per specifications.

Fig. 13. Semi-log graph (f_n_ in log scale) of the theoretical dc output voltage V_out_ versus the normalized switching frequency f_n_ of the designed converter.

Figure 14 shows the converter primary-side and secondary-side waveforms when maximum input voltage Vin, max (370 V) is applied to the converter under the no-load condition. The output voltage is successfully regulated at the minimum value Vout, min (35 V) through employing the maximum switching frequency fn, max.

Fig. 14. Simulation Waveforms at No load and V_in, max_ = 370 V, (a) Mosfet Gate voltages for M1 V_GS, M1_ and M2 V_GS, M2_, (b) MOSFET M1 drain-source voltage V_DS, M1_ and drain-source current I_DS, M1_, (c) Resonant Tank input voltage V_DS, M2_ and input current I_Lr_, (d) Rectifier current for Diode D1 I_D1_ and Diode D2 I_D2_, (e) Diode D1 voltage V_D1_ and current I_D1_, (f) Load Voltage V_out_ and current I_RL_.

Figure 15 illustrates the converter primary-side and secondary-side waveforms to deliver maximum power to the output load (Full-load condition) when minimum input voltage Vin, min (320 V) is applied to the converter. As shown in this figure, the maximum output voltage Vout, max (165 V) is achieved through employing the minimum switching frequency fn, min.

Fig. 15. Simulation Waveforms at Full Load and V_in, min_ = 320 V, (a) Mosfet Gate voltages for M1 V_GS, M1_ and M2 V_GS, M2_, (b) MOSFET M1 drain-source voltage V_DS, M1_ and drain-source current I_DS, M1_, (c) Resonant Tank input voltage V_DS, M2_ and input current I_Lr_, (d) Rectifier current for Diode D1 I_D1_ and Diode D2 I_D2_, (e) Diode D1 voltage V_D1_ and current I_D1_, (f) Load Voltage V_out_ and current I_RL_.

To demonstrate the ZVS operation for the designed LLC converter, Fig. 16 shows the high side MOSFET (M1) drain to source voltage being reduced to zero before the gate voltage is applied. Hence, the ZVS operation is achieved even under the two worst-case scenarios. As shown in this figure, the dead-time must be chosen to be more than the time required for the MOSFET drain to source voltage to be reduced to zero, otherwise the ZVS property will be lost^9,10,19^. However, increasing the dead-time will result in lower efficiency, thus a design tradeoff. In this case, a deadtime of 350 ns was deemed adequate.

Fig. 16(LEFT) Simulation Waveforms at Full Load and V_in, min_ = 320 V. (a) MOSFET Gate voltages for M1 V_GS, M1_ and M2 V_GS, M2_, (b) MOSFET M1 drain-source voltage V_DS, M1_ and drain-source current I_DS, M1_, (c) Resonant Tank input voltage V_DS, M2_ and input current I_Lr_, (RIGHT) Simulation Waveforms at No load and V_in, max_ = 370 V. (d) MOSFET Gate voltages for M1 V_GS, M1_ and M2 V_GS, M2_, (e) MOSFET M1 drain-source voltage V_DS, M1_ and drain-source current I_DS, M1_, (f) Resonant Tank input voltage V_DS, M2_ and input current I_Lr_.

Figure 17 illustrates the converter efficiency versus its output power at Vin, min and Vout, max while the load resistance is changed in steps. According to this figure, at the full load, 495 W, an efficiency of 97.49% is achieved, while the absolute maximum efficiency is 97.76% achieved at an output power of 511 W. This means that the efficiency at the full load condition is less than the maximum efficiency by around 0.3%, this deviation can be explained as a consequence of the FHA method ignoring the harmonics and the underlying assumptions used in deriving (6). This result demonstrates that the designed converter successfully attained maximum efficiency near the full-load operating point.

Fig. 17. Efficiency η versus output power P_out_ at V_in, max_.

To validate the accuracy of the simulation results, a comparative study is summarized in Table 3 comparing the proposed and other published methods. For the comparison to be unbiased, the converters must be designed for the same operating conditions based on the same circuit topology and simulated using the same model. Thus, for each published method, a converter is designed using the proposed approach to operate in the same conditions with the same maximum switching frequency, then both are simulated at full load (minimum input voltage, maximum output voltage and maximum output current at the minimum switching frequency). Compared to the other methods, the proposed approach tends to improve efficiency while using lower switching frequency at full-load. However, this comes at the expense of higher Lr/Lm ratio and larger switching frequency range. The lower switching frequency at full-load is a direct consequence of choosing a small value for fn, min in Fig. 12. Accordingly, the switching frequency range can be reduced by choosing a higher value for fn, min .

Table 3. Comparative study using the same simulation model.MethodVout (V)Vin (V)Pout (W)Lr (uH)Lm (uH)Cr (nF) N F_s_ (KHz)Efficiency (%) ^10^ 35–165320–370495.132431616.62.33106–31596.58Proposed35–165320–370495.18487.4139.27.41.2481–31597.49 ^26^ 250–300300352.412.865006210.5100–17097.89Proposed250–300300353.3228.07140.031160.5280–17098.01

Conclusion

In this paper, a novel optimal design procedure for improving the efficiency of the LLC resonant converter at a specific load while operating over a wide output voltage range has been presented. Moreover, all possible circuit configurations that satisfy the wide output voltage range constraint, the ZVS condition for the whole operation, and the max efficiency at a predetermined output load have been identified. This approach simplifies the design of the converter to merely selecting the values of two independent parameters to be within some permissible parameter space and the rest of the converter parameters can be derived accordingly. Analytical expressions for the converter design parameters have been derived in closed form, which ensures that the converter design optimization can be done without the need of the slow and computationally expensive numerical optimization algorithms. Additionally, the design methodologies that rely on numerical optimization algorithms can benefit from the proposed method in selecting the initial circuit designs to be used as a starting point for these algorithms. Thus, ensuring that the initial designs are both feasible and near the optimal design, thereby reducing the time needed to reach the global optimal design of the LLC resonant converter.