# A fully integrated harmonic injection and envelope-tracking architecture to extend the linearity of RF power amplifiers under high PAPR

## TL;DR

This paper introduces a new RF power amplifier design that improves linearity and efficiency under high signal complexity using integrated harmonic injection and envelope tracking.

## Contribution

A novel harmonic injection technique and CMOS-integrated envelope-tracking modulator are proposed to enhance amplifier linearity and efficiency.

## Key findings

- The design achieves a 1.2 dB improvement in output saturation power and 4.4 dB in P1dB.
- Peak PAE improves by 12.5%, with a 14.6% increase in PAE at P1dB while maintaining EVM below 5%.
- A fully integrated on-chip inductor solution is enabled through mathematical analysis of inductor and switching frequency trade-offs.

## Abstract

High peak-to-average power ratio (PAPR) in modern modulation schemes causes power amplifier nonlinearity due to transistor saturation and results in considerable power loss. To mitigate these effects and extend the linear range, this work proposes a novel harmonic injection technique aimed at enhancing the 1-dB compression point. A new analytical model based on Taylor series expansion and drain current derivatives is developed, enabling a fully integrated injection scheme that avoids conventional components such as circulators or frequency doublers. A new biasing method is also derived from this model. To address power loss under high PAPR, a new fully CMOS-integrated hybrid envelope-tracking modulator is introduced. A custom-designed sensing circuit removes the need for sensing resistors and external voltage references, significantly reducing output ripple. Moreover, a new current management scheme is introduced that removes the ripple-filtering burden from the linear amplifier, simplifying its design. A comprehensive mathematical analysis is also provided to characterize the trade-offs between the inductor value and switching frequency, enabling a fully integrated on-chip inductor solution. Results in 180 nm CMOS show improvements of 1.2 dB in output saturation power, 4.4 dB in P1dB, and 12.5% in peak PAE. PAE at P1dB improves by 14.6%, with EVM remaining below 5%.