A Codesign Framework for the Development of Next Generation Wearable Computing Systems
Francesco Porreca, Fabio Frustaci, Raffaele Gravina
TL;DR
This paper introduces a new framework for designing wearable computing systems that balance power efficiency and performance using FPGAs and MCUs.
Contribution
A novel mixed FPGA/MCU development framework tailored for wearable systems is proposed and validated with real-world results.
Findings
The framework achieved significant improvements in execution speed for wearable computing tasks.
Power consumption was reduced, supporting the development of energy-efficient wearable systems.
The framework's versatility was confirmed through a real-world use case.
Abstract
Wearable devices can be developed using hardware platforms such as Application Specific Integrated Circuits (ASICs), Graphics Processing Units (GPUs), Digital Signal Processors (DSPs), Micro controller Units (MCUs), or Field Programmable Gate Arrays (FPGAs), each with distinct advantages and limitations. ASICs offer high efficiency but lack flexibility. GPUs excel in parallel processing but consume significant power. DSPs are optimized for signal processing but are limited in versatility. CPUs provide low power consumption but lack computational power. FPGAs are highly flexible, enabling powerful parallel processing at lower energy costs than GPUs but with higher resource demands than ASICs. The combined use of FPGAs and CPUs balances power efficiency and computational capability, making it ideal for wearable systems requiring complex algorithms in far-edge computing, where data…
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Taxonomy
TopicsGreen IT and Sustainability · Embedded Systems Design Techniques · Context-Aware Activity Recognition Systems