A CMOS Voltage Reference with PTAT Current Using DIBL Compensation for Low Line Sensitivity
Minji Jung, Youngwoo Ji
TL;DR
This paper introduces a low-power CMOS voltage reference with improved sensitivity to supply voltage changes.
Contribution
A novel DIBL-based compensation path is used to reduce line sensitivity in PTAT current generation.
Findings
The circuit achieves 0.01%/V line sensitivity for the voltage reference.
It consumes 68 nW while generating a 538 mV reference voltage and 38 nA PTAT current.
The temperature coefficient is 58 ppm/℃ over a wide temperature range.
Abstract
This paper presents a low-power CMOS voltage reference with low supply sensitivity, designed and verified in a 180 nm standard CMOS technology. A DIBL-based line-sensitivity (LS) compensation path is incorporated into the conventional PTAT generation circuit to simultaneously provide a reference voltage and a bias current with improved LS. The proposed circuit achieves LS values of 0.01%/V for the voltage reference and 0.07%/V for the bias current reference over a supply voltage range of 1.4 V to 2 V. It generates a reference voltage of 538 mV and a PTAT current of 38 nA, consuming 68 nW. The simulated temperature coefficient is 58 ppm/℃ from −40 °C to 130 °C, and the power supply rejection ratio is −59 dB at 100 Hz.
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Taxonomy
TopicsAnalog and Mixed-Signal Circuit Design · Low-power high-performance VLSI design · Innovative Energy Harvesting Technologies