# Pipelined and conflict-free number theoretic transform accelerator for CRYSTALS-Kyber on FPGA

## TL;DR

This paper presents an optimized FPGA-based hardware accelerator for the CRYSTALS-Kyber post-quantum encryption algorithm.

## Contribution

A pipelined and conflict-free NTT core with improved resource efficiency and ATP performance for Kyber on FPGA.

## Key findings

- The design achieves a 7.8% reduction in FPGA resources compared to existing implementations.
- The Area-Time Product (ATP) is improved by 49.6% over state-of-the-art designs.
- The implementation uses algorithmic and architectural optimizations like multiplier-less Montgomery reduction.

## Abstract

Post-quantum cryptographic (PQC) algorithms are essential due to the threat posed by quantum computers to the security of currently deployed cryptosystems. CRYSTALS-Kyber, based on Lattice-based cryptography, has been standardized as the Public-Key Encryption and Key-Establishment Mechanism Algorithm by the National Institute of Standards and Technology (NIST). An efficient hardware acceleration of CRYSTALS-Kyber relies on optimizing the computationally intensive Polynomial Multiplication Number Theoretic Transform (NTT) unit. This work presents an FPGA implementation of conflict-free and pipelined single-path delay feedback based NTT core for Kyber by employing various architectural optimizations including pipelining, resource sharing and algorithmic optimizations like multiplier-less Montgomery reduction algorithm. As a result, our design has 7.8% reduction in resources and 49.6% improved Area-Time Product (ATP) as compared to the state-of-the-art designs. The presented architectures are coded using Verilog HDL and implemented on Xilinx Artix-7 XC7A100T-3 and Virtex-7 XC7VX485T-3 devices using Vivado Design Suite 2022.2.