# A 1.2-V 7.76-ENOB 1-MS/s single-ended SAR ADC in 65-nm CMOS for biomedical applications

## TL;DR

This paper presents a low-power, high-performance SAR ADC designed for biomedical applications using a 65-nm CMOS process.

## Contribution

The paper introduces a novel SAR ADC with improved energy efficiency and performance through hardware optimizations.

## Key findings

- The proposed ADC achieves 7.76 effective number of bits (ENOB) at 1 MS/s.
- Power consumption is reduced by 7.5% using a modified dynamic latch comparator.
- The design saves 36.7% power in the capacitive DAC compared to conventional designs.

## Abstract

A successive approximation register analog-to-digital converter (SAR ADC) is a promising approach used in biomedical applications due to its energy-efficiency architecture with less complex hardware implementation. The core building blocks of SAR ADC are sample-and-hold switch (S/H), comparator, logic control register, and digital-to-analog converter (DAC). To enhance the overall performance, a high-isolation CMOS bootstrap S/H switch has been used. The SFDR of proposed ADC has increased by up to 2.2 dB. Also, we propose a double-tail single-ended dynamic latch comparator with extra pair PMOS transistors that save power by up to 7.5% as compared to the traditional double-tail dynamic comparator. Moreover, after adding these pair of transistors into conventional double tail dynamic comparator without any calibration cost, the SNDR has increased by more than 2 dB and 0.3bit improvement of ENOB. Furthermore, a synchronous modified SAR logic control register based on low-power D flip-flops (FFs) is proposed. A metal-isolator-metal capacitor (MIM) with a modified capacitance reduction configuration is used to improve the active area of the capacitive DAC (CDAC) compared to the conventional CDAC with 36.7% saving power. The proposed ADC has been implemented using a 65-nm TSMC CMOS process, 1.2 V supply voltage with a sampling rate of 1 MS/s. An active area of 0.00585 mm2 with a total post-result power consumption of 5.75 µW has been accomplished for the proposed fully integrated ADC.