# Reduction Method for a Network-on-Chip Low-Level Modeling

## TL;DR

This paper introduces a method to simplify the modeling of networks-on-chip by replacing IP blocks with data packet generators, improving simulation efficiency and scalability.

## Contribution

A novel low-level NoC modeling method using data packet generators and a universal interface to reduce resource costs and improve simulation speed.

## Key findings

- Replacing IP blocks with data packet generators increases the maximum number of nodes in simulated NoCs.
- The universal interface reduces connection resource costs and configuration time for new components.
- The method effectively supports analysis of routing algorithms across various network topologies.

## Abstract

This article explores the concept of low-level modeling of networks-on-chip (NoCs). A method for reducing the low-level NoC model by replacing the real IP blocks with a data packet generator module is proposed. This method is implemented in the low-level NoC modeling ECAD tool HDLNoCGen. This makes it possible to significantly increase the maximum number of nodes in the simulated NoC, as well as speed up the modeling and investigate the resource costs for network synthesis. A universal interface that can be used to connect new components to the network is also described. This interface has two main benefits: it reduces connection resource costs by eliminating the need to modify the connected component and shortens the time required to configure the connection interface itself. The proposed methodology of low-level NoC modeling is shown to be effective in analyzing the operation of routing algorithms of the NoC communication subsystem based on various topologies.