# Large‐Scale Implementation of Vertical Sidewall and Vertical Multi‐Channel WS2 Nanosheet Field‐Effect Transistors for Area‐Efficient Integrated Circuit

## TL;DR

Researchers developed ultra-compact transistors using WS2 nanosheets, enabling efficient and scalable integrated circuits.

## Contribution

First demonstration of vertical multi-channel WS2 nanosheet FETs with improved performance and area efficiency.

## Key findings

- Vertical WS2 FETs achieved subthreshold swing and suppressed short-channel effects at 150 nm channel lengths.
- Integration of logic gates and SRAM using vertical and planar WS2 FETs confirmed scalability.
- Vertical multi-channel NSFETs showed improved drive current with gate-all-around-like structures.

## Abstract

2D materials have emerged as promising candidates for next‐generation field‐effect transistors (FETs) owing to the atomically thin geometry and excellent electrostatic gate control. Here, double‐gate vertical sidewall FETs based on chemical vapor deposition‐grown monolayer WS2 are demonstrated and, for the first time, report vertical multi‐channel nanosheet FETs (NSFETs). By implementing a dual‐step sidewall profile, steep SiO2 surfaces are obtained, which enabled seamless WS2 adhesion and contributed to enhanced device yield. The fabricated vertical sidewall WS2 FETs exhibited good subthreshold swing (SS) and effectively suppressed short‐channel effects at channel length as short as 150 nm. Logic gates including inverters, NAND, NOR, AND, OR, and SRAM are integrated using vertical sidewall and planar WS2 FETs, validating the feasibility of area‐efficient integrated circuit. Furthermore, improved drive current is achieved in vertical multi‐channel NSFETs realized by stacking WS2 channels and employing a gate‐all‐around–like structure. These results highlight the potential of vertical sidewall FETs for enabling area‐efficient, ultra‐dense integrated circuits.

In this work, the authors successfully demonstrate double‐gate vertical sidewall WS2 FETs and, for the first time, vertical multi‐channel WS2 NSFETs using CVD‐grown monolayer WS2. By optimizing dual‐step SiO2 sidewall profiles and employing high‐κ dielectrics, they achieve excellent subthreshold swing, suppressed short‐channel effects, and high I
ON/I
OFF ratios down to 150 nm channel lengths. Furthermore, area‐efficient logic gates and SRAM circuits are realized by integrating vertical sidewall and planar WS2 FETs, highlighting the scalability and potential of vertical 2D FET architectures for ultra‐dense integrated circuits.