An Area-Efficient Readout Circuit for a High-SNR Triple-Gain LOFIC CMOS Image Sensor

TL;DR

This paper introduces a more efficient readout circuit for a high-performance image sensor that improves image quality and reduces noise.

Contribution

The novel triple-gain LOFIC CIS readout circuit uses amplifier and capacitor sharing to improve SNR and reduce area overhead.

Findings

The proposed readout circuit achieved an 8.05 dB improvement in SNR drop at the gain switching point.

The area overhead of the new circuit was only 7.6%.

The circuit was fabricated using a 0.18μm CMOS process.

Abstract

A lateral overflow integration capacitor (LOFIC) CMOS image sensor (CIS) can achieve high-dynamic-range (HDR) imaging by combining a low-conversion-gain (LCG) signal with a high-conversion-gain (HCG) signal. However, the signal-to-noise ratio (SNR) drops at the switching point from HCG signal to LCG signal due to the significant pixel noise in the LCG signal. To address this issue, a triple-gain LOFIC CIS with a middle-conversion-gain (MCG) signal has been introduced. In this work, we propose an area-efficient readout circuit for the triple-gain LOFIC CIS, using amplifier and capacitor sharing techniques to process the HCG, MCG, and LCG signals. A test chip of the proposed readout circuit was fabricated using the 0.18μm CMOS process. The area overhead was only 7.6%, and the SNR drop was improved by 8.05 dB compared to the readout circuit for a dual-gain LOFIC CIS.

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Full text

1. Introduction

CMOS image sensors (CISs) used in conditions of extreme illumination (e.g., outside) require high-dynamic-range (HDR) imaging technology to avoid underexposure and overexposure of various objects in a scene. Many approaches have been proposed to realize HDR CISs, such as logarithmic compression [1,2], multiple-exposure HDR (MEHDR) [3,4,5,6], dual-conversion-gain (DCG) pixels [7,8,9,10,11,12], and lateral overflow integration capacitor (LOFIC) pixels [7,13,14,15,16,17,18,19,20,21]. LOFIC pixels promise a linear response and reduced motion artifacts. MEHDR images that combine two images taken at different exposure times will cause motion artifacts due to the misalignment of the timings. On the other hand, SEHDR systems, such as LOFIC, combine two images taken at the same exposure time with different gains: low conversion gain (LCG) and high conversion gain (HCG). Thus, SEHDR has an advantage for mitigating motion artifacts [22]. The LOFIC pixel uses an LCG signal to process large maximum signal charges and an HCG signal to reduce dark noise for HDR imaging. However, the LCG pixel reset noise is not canceled due to uncorrelated double sampling, while the HCG pixel reset noise is canceled by correlated double sampling (CDS). Consequently, the signal-to-noise ratio (SNR) drops at the switching point from an HCG to LCG signal. The SNR drop can be mitigated by adding a middle-conversion-gain (MCG) signal, which shifts the switching point of the LCG signal towards a higher signal level. Although several architectures using MCG signals [19,20,21,23] have been proposed, these studies have primarily focused on increasing the dynamic range by enlarging the pixel size or reducing motion artifacts. Additionally, the peripheral circuit area is large because a three-channel readout circuit is required to read the HCG, MCG, and LCG signals [24]. In this work, we propose an area-efficient readout circuit for the triple-gain LOFIC CIS by using amplifier and capacitor sharing techniques based on our previous design for a conventional dual-gain LOFIC CIS [25]. The proposed readout circuit is designed to minimize the SNR drop while maintaining a small pixel area and suppressing motion artifacts. A test chip of the readout circuit was fabricated using a $[eqn]$ m CMOS process and was evaluated to estimate the SNR. Our contributions are summarized as follows:

• To mitigate the SNR drop, we propose the triple-gain LOFIC CIS without enlarging the pixel area or degrading motion artifacts.
• We propose a readout circuit that is area-efficient for the triple-gain LOFIC CIS.
• We evaluate a fabricated test chip and estimate the SNR.

Section 2 provides a voltage-level diagram for designing a triple-gain readout circuit for an LOFIC pixel. The proposed readout circuit is described in Section 3, followed by the measurement results of a fabricated test chip shown in Section 4. Section 5 provides a summary of this work.

Updates from the Conference Proceeding

A conference proceeding version of this paper appeared in the 2025 IEEE International Symposium on Circuits and Systems (ISCAS) [26], and this extended version contains the following new content:

• Pixel- and circuit-gain combination for the MCG signal (Section 2.1, Figure 1).
• Details of the baseline circuit and comparison with the proposed readout circuit (Section 3.1, Figure 3).
• Noise analysis of baseline circuit and proposed readout circuit (Figure 4 and Figure 6).
• A discussion of this study and a comparison with other works (Section 4).

2. Concept-Level Design

This section presents a method to generate the MCG signal, in addition to the conventional HCG and LCG signals, without increasing the pixel area. The MCG signal can be obtained either by combining a high pixel gain with a low circuit gain or a low pixel gain with a high circuit gain. First, the combination for the MCG signal is determined based on the circuit noise performance. Then, a voltage-level diagram is examined for the triple-gain LOFIC CIS using the selected MCG configuration.

2.1. Pixel- and Circuit-Gain Combination for the MCG Signal

In our conventional dual-gain LOFIC CIS [25], the HCG signal is generated by a high pixel gain and a high circuit gain, while the LCG signal is generated by a low pixel gain and a low circuit gain, as shown in Figure 1. The full well capacity (FWC) for HCG signal is $[eqn]$ , provided by $[eqn]$ / $[eqn]$ / $[eqn]$ , where $[eqn]$ is a maximum output signal of $[eqn]$ V; $[eqn]$ and $[eqn]$ are circuit gain, including a pixel source-follower (SF) gain of $[eqn]$ and a pixel conversion gain of $[eqn]$ [16], respectively. The floor noise for HCG signal is $[eqn]$ , provided by N/ $[eqn]$ / $[eqn]$ , where N is the output floor noise of $[eqn]$ based on previous work [25]. While the input-referred noise is very small, the FWC is limited. Similarly, the FWC for LCG signal is $[eqn]$ , provided by $[eqn]$ / $[eqn]$ / $[eqn]$ , where $[eqn]$ is a maximum output signal of $[eqn]$ V; $[eqn]$ and $[eqn]$ are circuit gain, including a pixel SF gain of $[eqn]$ and a pixel conversion gain of $[eqn]$ [16], respectively. The floor noise for LCG signal is $[eqn]$ , provided by N/ $[eqn]$ / $[eqn]$ , where N is the output floor noise of $[eqn]$ based on previous work [25]. While the FWC is very large, the input-referred noise is considerably large. Thus, the signal-to-noise ratio (SNR) at the switching point from the HCG to LCG signal is provided by $[eqn]$ dB, where the noise will be visible because the SNR is below 30 dB [27].

To generate the MCG signal, two candidates are considered: (1) high pixel gain combined with low circuit gain; and (2) low pixel gain combined with high circuit gain. This is because the selectable pixel gain is constrained to either high or low in order to maintain a compact pixel area, as in the conventional dual-gain LOFIC pixels [16]. The FWC for MCG (1) signal is $[eqn]$ , provided by $[eqn]$ / $[eqn]$ / $[eqn]$ , where $[eqn]$ is a maximum output signal of $[eqn]$ V; $[eqn]$ and $[eqn]$ are circuit gain, including a pixel SF of $[eqn]$ and a pixel conversion gain of $[eqn]$ [16], respectively. The floor noise for MCG (1) signal is $[eqn]$ , provided by N/ $[eqn]$ / $[eqn]$ , where N is the output floor noise of $[eqn]$ based on previous work [25]. The SNR at the switching point from HCG to MCG (1) is $[eqn]$ dB. On the other hand, the SNR at the switching point from MCG (1) to LCG is $[eqn]$ dB. Similarly, the input FWC values of MCG (2) are $[eqn]$ , provided by $[eqn]$ / $[eqn]$ / $[eqn]$ , where $[eqn]$ is a maximum output signal of $[eqn]$ V; $[eqn]$ and $[eqn]$ are circuit gain, including pixel SF of $[eqn]$ and a pixel conversion gain of $[eqn]$ [16], respectively. The floor noise for MCG (2) signal is $[eqn]$ , provided by N/ $[eqn]$ / $[eqn]$ , where N is the output floor noise of $[eqn]$ based on previous work [25]. The SNR at the switching point from HCG to MCG (2) is $[eqn]$ dB. On the other hand, the SNR at the switching point from MCG (2) to LCG is $[eqn]$ dB. Based on these rough estimations, MCG (1) is selected because of its larger margin relative to the 30 dB criterion. Additionally, it is noted that photon shot noise dominates at the switching point to the LCG signal.

2.2. Voltage-Level Diagram

For the triple-gain LOFIC CIS employing the selected MCG configuration, combining the high pixel gain with the low circuit gain, a detailed voltage-level diagram was designed, as shown in Figure 2, including the pinning voltage of the photo-diode (PD) ( $[eqn]$ ), the signal voltage swing at the floating diffusion (FD) node ( $[eqn]$ ) and at the pixel output ( $[eqn]$ ), and the input to an ADC ( $[eqn]$ ). For the HCG signal shown in Figure 2a, the voltage gain of the double-sampling (DS) circuit is selected as $[eqn]$ , such that the input-referred circuit noise can be decreased and a high dynamic range can be achieved. The input window of the DS circuit, which derives from the difference between the reset level and the signal level from the pixel output, is set to $[eqn]$ V for the $[eqn]$ V ADC input window [28], and the signal voltage swing at the FD node is limited to below $[eqn]$ V with a $[eqn]$ SF gain. For the MCG signal shown in Figure 2b, the PD FWC and $[eqn]$ are assumed to be $[eqn]$ [16] and 1 fF, respectively, and the maximum signal voltage swing at the FD node is $[eqn]$ V. Even though the clock feed-through on a small $[eqn]$ can be as large as $[eqn]$ V when the $[eqn]$ is turned off, there is still a sufficient voltage margin to transfer the photo-electrons integrated in the PD to the FD node. The input window of the DS circuit is $[eqn]$ V with an SF, and the voltage gain of the DS circuit is set to $[eqn]$ for the ADC input window. For the LCG signal shown in Figure 2c, the maximum voltage swing at the FD node is set to $[eqn]$ V in order to read the photo-electrons integrated in the PD, FD, and $[eqn]$ . The input window of the DS circuit is set to $[eqn]$ V with an SF, and the gain of the DS circuit is set to $[eqn]$ for the ADC input window. The clock feed-through on $[eqn]$ and $[eqn]$ is as small as $[eqn]$ V when the $[eqn]$ is turned off. Hence, the voltage margin required to transfer the photo-electrons integrated in the PD to the FD node remains even for large-FD voltage swings. These level diagrams show that the HCG and MCG signals are inverted, while the LCG signal is not, which enables sharing an ADC for the triple-gain signals.

3. Proposed Readout Circuit for a Triple-Gain LOFIC CIS

As the three-channel readout circuit [24] used to read HCG, MCG, and LCG signals in triple-gain LOFIC CIS leads to an increased chip size, we propose a single-channel readout circuit for the triple-gain LOFIC CIS. First, a baseline circuit is presented, followed by an enhanced design aimed at reducing circuit noise.

3.1. Baseline Readout Circuit

A baseline readout circuit for the triple-gain LOFIC CIS is shown in Figure 3. An amplifier and capacitor are shared for the HCG and MCG signals, and an attenuation capacitor for the LCG signal is shared with a sampling capacitor of an ADC, in which the ADC subsequently processes the HCG, MCG, and LCG signals. This baseline readout circuit is based on our previous design for a conventional dual-gain LOFIC CIS [25], with only one additional feedback capacitor $[eqn]$ [29,30] introduced to implement the inverted attenuator for the MCG signal. Figure 3b shows a timing diagram of the baseline readout circuit. The total conversion period is $[eqn]$ s and has increased by $[eqn]$ s compared to dual-gain LOFIC CIS [25] but remains less than 1.5 times. First, $[eqn]$ , $[eqn]$ , and $[eqn]$ are all toggled to reset the PD, the floating diffusion capacitor $[eqn]$ , and an overflow photo-electron integration capacitor $[eqn]$ at $[eqn]$ prior to starting the exposure. When the exposure is complete, $[eqn]$ becomes high in a given pixel row, and the pixel reset levels for HCG and MCG ( $[eqn]$ ) are output from the selected pixel at $[eqn]$ . At this time, $[eqn]$ values are high to store $[eqn]$ in $[eqn]$ , where $[eqn]$ and $[eqn]$ are the pixel SF gain and the offset of the pixel SF transistor, respectively. The amplifier reset noise, $[eqn]$ , is generated on the virtual ground node, and $[eqn]$ is sampled in $[eqn]$ after $[eqn]$ is turned off at $[eqn]$ . Figure 4a shows the equivalent circuits at $[eqn]$ , where the bias voltage $[eqn]$ and noise other than the amplifier reset noise are considered to be 0 for simplicity.

By toggling $[eqn]$ at $[eqn]$ , the pixel signal levels for HCG and MCG ( $[eqn]$ ), provided by $[eqn]$ , where $[eqn]$ is the signal charge transferred from the PD, are output from the pixel at $[eqn]$ . Figure 4b shows the equivalent circuits at $[eqn]$ . At this time, the output signal from the amplifier, $[eqn]$ , is inverted and amplified using $[eqn]$ and $[eqn]$ , as provided by

$$[eqn]$$

The HCG signal input to the ADC, $[eqn]$ , is thus provided by

$$[eqn]$$ $$[eqn]$$

where the amplifier reset noise $[eqn]$ is removed. Subtracting the pixel reset level from the pixel signal level also cancels the pixel reset noise and the offset of the pixel SF transistor $[eqn]$ . After $[eqn]$ becomes high, where Figure 4c is the equivalent circuit, the output signal from amplifier, $[eqn]$ , is provided by

$$[eqn]$$

at $[eqn]$ . The MCG signal input to the ADC, $[eqn]$ , is inverted and attenuated, as provided by

$$[eqn]$$ $$[eqn]$$

As provided by Equation (6), the amplifier reset noise for the MCG signal is not canceled, which decreases its SNR, resulting in an SNR drop from HCG to MCG. After $[eqn]$ and $[eqn]$ become high, the pixel signal level for LCG ( $[eqn]$ ), provided by $[eqn]$ , is directly stored in $[eqn]$ at $[eqn]$ . After $[eqn]$ is toggled to reset $[eqn]$ and $[eqn]$ , the pixel reset level for LCG, provided by $[eqn]$ , is output from the pixel array. The non-inverted and attenuated LCG signal, using $[eqn]$ and $[eqn]$ , is input to the ADC at $[eqn]$ , as provided by

$$[eqn]$$ $$[eqn]$$

The voltage difference between $[eqn]$ and $[eqn]$ results in high pixel reset noise $[eqn]$ , provided by $[eqn]$ . The pixel reset noise $[eqn]$ is estimated to be $[eqn]$ , assuming $[eqn]$ and $[eqn]$ [16]. LCG pixel reset noise $[eqn]$ is not canceled. The SNR of LCG signal is high since LCG has a large signal electron, even if the pixel reset noise $[eqn]$ is not canceled. However, the impact of the pixel reset noise $[eqn]$ is significant with a small signal electron, leading to the SNR drop. By adding MCG signal, the switching point of the LCG signal shifts towards a higher signal level, resulting in suppression of the SNR drop.

3.2. Proposed Circuit

Although the baseline circuit is area-efficient, it does not cancel the amplifier reset noise for the MCG signal, as provided by Equation (6). This causes an SNR drop from HCG to MCG. To solve this problem, we propose a readout circuit, as shown in Figure 5a, consisting of the same capacitance as the baseline circuit. The changes from the baseline circuit are indicated by red lines. Figure 5b shows a timing diagram of the proposed readout circuit. At $[eqn]$ , $[eqn]$ and $[eqn]$ are high, and $[eqn]$ is stored in $[eqn]$ and $[eqn]$ , respectively. The amplifier reset noise, $[eqn]$ , is sampled in $[eqn]$ after $[eqn]$ is turned off at $[eqn]$ . Figure 6a shows the equivalent circuits at $[eqn]$ , where $[eqn]$ and noise other than the amplifier reset noise are considered to be 0 for simplicity.

After $[eqn]$ becomes low and $[eqn]$ is transferred from the PD at $[eqn]$ , the pixel signal levels for HCG and MCG ( $[eqn]$ ) are output from the pixel at $[eqn]$ , as shown in Figure 6b. At this time, the output signal from amplifier, $[eqn]$ , is inverted and amplified using $[eqn]$ and $[eqn]$ , as provided by

$$[eqn]$$

The HCG signal input to the ADC, $[eqn]$ , is thus provided by

$$[eqn]$$ $$[eqn]$$

The amplifier reset noise is canceled for the HCG signal, as in the baseline circuit. Before reading out the MCG signal, $[eqn]$ becomes high, and $[eqn]$ is toggled to reset the charge stored in $[eqn]$ and $[eqn]$ at $[eqn]$ . At this time, the amplifier reset noise $[eqn]$ is generated, and $[eqn]$ is sampled in $[eqn]$ after $[eqn]$ is turned off at $[eqn]$ . At this time, $[eqn]$ is high to set $[eqn]$ as a sampling capacitor and to reuse $[eqn]$ as a feedback capacitor, respectively. The equivalent circuit at $[eqn]$ is shown in Figure 6c. The output signal from amplifier, $[eqn]$ , is inverted and attenuated using $[eqn]$ and $[eqn]$ , as provided by

$$[eqn]$$

The MCG signal input to the ADC, $[eqn]$ , is thus provided by

$$[eqn]$$ $$[eqn]$$

Due to autozeroing before readout of the MCG signal, the amplifier reset noise is also canceled for the MCG signal. The operation from $[eqn]$ to $[eqn]$ is the same as that described for the baseline circuit from $[eqn]$ to $[eqn]$ .

4. Fabrication and Evaluation of a Test Chip

A test chip of the proposed readout circuit for the triple-gain LOFIC CIS was fabricated using a $[eqn]$ 1P5M CMOS process with MIM capacitors. A photo of the fabricated test chip is shown in Figure 7. The test chip contains the DS circuit, 10-bit SAR-ADC, BIAS, and BUFFER. The LOFIC pixel was not implemented in the test chip. There are 86 columns of DS circuits and ADCs with a pitch of $[eqn]$ m laid out in parallel. The circuit area for the triple-gain LOFIC CIS increased by only $[eqn]$ compared to the readout circuit for the dual-gain LOFIC CIS [25].

Figure 8 shows the measured input and output characteristics of the HCG, MCG, and LCG signals when the power supply voltage $[eqn]$ is set to $[eqn]$ V. The X-axis represents the voltage difference between the pixel reset level and signal level, and the Y-axis represents the output voltage swing referred from the ADC output. The measured circuit gains of the HCG and MCG signals were $[eqn]$ and $[eqn]$ , respectively. These values were lower than the target values of $[eqn]$ and $[eqn]$ , respectively. The root cause is suspected to be parasitic capacitance. The measured gain of the LCG signal was $[eqn]$ , which was also lower than the target value of $[eqn]$ . Table 1 summarizes the measured circuit gain and the estimated total gain. The estimated total gain is provided by $[eqn]$ , where $[eqn]$ represents the measured circuit gains, such as 5.67 for HCG, 0.76 for MCG, or 0.62 for LCG; $[eqn]$ represents the pixel conversion gains of $[eqn]$ for HCG and MCG and $[eqn]$ for LCG [16]; and $[eqn]$ is the pixel SF gain of $[eqn]$ , respectively.

The measured input-referred circuit noise is $[eqn]$ , $[eqn]$ , and $[eqn]$ for the HCG, MCG, and LCG signals, respectively, provided by $[eqn]$ / $[eqn]$ / $[eqn]$ , where $[eqn]$ is the measured output noise from readout circuit, $[eqn]$ is the measured circuit gain, and $[eqn]$ is pixel SF gain, respectively. The estimated input-referred noise is provided by $[eqn]$ / $[eqn]$ , where $[eqn]$ is the measured input-referred circuit noise and $[eqn]$ is pixel conversion gain [16], respectively. The input-referred circuit noise for the LOFIC pixel is also summarized in Table 2. For HCG, the input-referred circuit noise is minimized thanks to both high circuit gain and high pixel gain. Similarly, the input-referred circuit noise for MCG is lower than that for LCG thanks to its higher pixel gain even though the measured noise for MCG is greater than that for LCG because of the additional inverting attenuator.

Figure 9 shows the SNR, which takes into account the theoretical optical shot noise, the theoretical pixel reset noise, and the measured noise of the proposed readout circuit. It is noted that the 1/f noise generated by the pixel SF transistor is mitigated through double sampling for the HCG, MCG, and LCG signals.

At the switching point from HCG to MCG, the SNR drop is only $[eqn]$ dB, which is very small, because the optical shot noise is dominant. The SNR drop at the switching point from MCG to LCG is $[eqn]$ dB, but this will not be visible because the SNR exceeds 30 dB [27]. As the estimated SNR drop for the dual-gain LOFIC CIS is $[eqn]$ dB, the proposed readout circuit improves the SNR drop by $[eqn]$ dB for the triple-gain LOFIC CIS.

Discussion

In the test chip design, 10-bit ADC was implemented. For HCG signal, the total conversion gain is $[eqn]$ , which is based on the following parameters; a pixel conversion gain of $[eqn]$ [16], a circuit gain including a pixel SF gain of $[eqn]$ , and ADC input window of $[eqn]$ V for 1024 LSB. Therefore, the quantization noise of the readout circuit is less than one electron. Although a 12-bit ADC is preferable, a 10-bit ADC remains acceptable to meet the performance requirements of our target LOFIC CIS.

Also in the test chip design, the conversion period is constrained by the A/D conversion period, which is limited by the maximum clock frequency of the test chip. However, it is estimated that a 2 Mpixel triple-gain LOFIC CIS can achieve a frame rate of approximately 45 fps when used with a high-speed ADC originally designed for a 2 Mpixel 60 fps dual-conversion-gain CMOS image sensor [31].

Although the readout circuit for the LOFIC pixel has rarely been addressed in the published literature, we have provided a specification and performance comparison, as shown in Table 3. The readout circuit for a triple-gain LOFIC CIS reported in [24] employs a three-channel architecture. The single-channel readout circuit used in a global-shutter CMOS image sensor with in-pixel dual storage [32] can be applied to LOFIC CIS. However, since autozeroing of the comparator in the ADC is not feasible for the LCG signal, offset errors may lead to column fixed-pattern noise at the switching point to the LCG signal. The proposed triple-gain readout circuit improves the signal-to-noise ratio (SNR) by $[eqn]$ dB, with no increase in pixel area, a $[eqn]$ increase in circuit area, and a $[eqn]$ reduction in frame rate compared to the case of a dual-gain readout circuit. The triple-gain LOFIC CIS incorporating the proposed readcout circuit will be suitable for cost-sensitive applications such as dashboard cameras and surveillance cameras.

5. Summary

We proposed an area-efficient readout circuit for the triple-gain LOFIC CIS in order to achieve a high SNR. The proposed readout circuit consists of an inverting amplifier, an inverting attenuator, a non-inverting attenuator, and an ADC. By utilizing amplifier and capacitor sharing techniques throughout the readout circuit, the area overhead of the readout circuit for the triple-gain LOFIC CIS is only $[eqn]$ compared to that of the dual-gain LOFIC CIS. The SNR drops at the switching points from the HCG to MCG signals and from the MCG to LCG signals are $[eqn]$ dB and $[eqn]$ dB, respectively, representing an improvement of up to $[eqn]$ dB. In future work, we will further evaluate the chip, including the LOFIC pixels.