# Design and fabrication of 4 double input NAND gate chip with excellent electrical and physical performances

## TL;DR

This paper presents a new 4-input NAND gate chip designed for aerospace and harsh environments with improved electrical and physical performance.

## Contribution

A novel 4-input NAND gate chip was designed and fabricated using a 1.2 μm CMOS process with enhanced ESD protection and anti-locking capabilities.

## Key findings

- The chip was fabricated using 1.2 μm P-well SPDM CMOS technology for improved performance.
- An ESD protection circuit was added to prevent input terminal damage from electrostatic discharge.
- The device's performance exceeds that of similar products globally.

## Abstract

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