The Impact of Single-Event Radiation on Latch-Up Effect in High-Temperature CMOS Devices and Its Mechanism

TL;DR

This study explores how high temperatures and radiation affect the latch-up behavior in CMOS devices, revealing significant changes in performance thresholds.

Contribution

The paper reveals the physical mechanism of single-event latch-up in high-temperature CMOS devices using TCAD simulations.

Findings

At 400 K, CMOS devices show a significant latch-up effect that increases with temperature.

The LET threshold for SEL decreases by 91.4% at 450 K compared to 300 K.

Latch-up trigger current and hold voltage decrease with increasing temperature.

Abstract

This paper investigates the latch-up effect in CMOS devices based on a 28 nm CMOS process within the temperature range of 200 K to 450 K using Sentaurus Technology Computer-Aided Design (TCAD) simulation, with a particular focus on the single-event latch-up (SEL) effect in the high-temperature range of 300 K to 450 K. The physical mechanism underlying the triggering of SEL in CMOS devices at high temperatures is revealed. The results show that when the linear energy transfer (LET) value is 75 MeV cm2/mg, the CMOS devices do not exhibit SEL effects at 300 K and 350 K. However, when the temperature rises to 400 K, a significant latch-up effect occurs, which becomes more pronounced with increasing temperature. Additionally, at a supply voltage of 1.2 V and a temperature of 450 K, the LET threshold for triggering SEL in CMOS devices decreases by 91.4% compared to 75 MeV cm2/mg at 300 K, dropping to 6 MeV cm2/mg. As the temperature increases, the latch-up trigger current of the CMOS devices decreases from 1.18 × 10−4 A/μm at 300 K to 4.65 × 10−5 A/μm at 450 K, and the hold voltage decreases from 1.48 V at 300 K to 1.07 V at 450 K.

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