# A High Dynamic Range and Fast Response Logarithmic Amplifier Employing Slope-Adjustment and Power-Down Mode

## TL;DR

This paper presents a fast and high dynamic range logarithmic amplifier with adjustable slope and low power consumption in standby mode.

## Contribution

The novel log slope adjuster and power-down mode enable flexible and energy-efficient logarithmic amplification.

## Key findings

- The amplifier achieves a dynamic range exceeding 80 dB with a 3 dB bandwidth of 20 MHz–4 GHz.
- It has a fast response time of 42 ns and consumes 109 mW in normal operation.
- Power consumption drops to 162 μW in standby mode using the power-down control unit.

## Abstract

Based on the GSMC 180 nm SiGe BiCMOS process, a parallel-summation logarithmic amplifier is presented in this paper. The logarithmic amplifier adopts a cascaded structure of nine-stage fully-differential limiting amplifiers (LA) to achieve high dynamic range. The ten-stage rectifier completes the conversion of amplified voltage to a logarithmic current signal. A log slope adjuster is proposed. It can provide slopes of 17–30 mV/dB by configuring an off-chip resistor to meet the detection requirements of different input power. Meanwhile, a power-down control unit is designed to reduce the power consumption to only 162 μW in standby mode. The post-simulation results show that under 5 V power supply voltage, the dynamic range exceeds 80 dB and the 3 dB bandwidth is 20 MHz–4 GHz. It also has a fast response time of 42 ns with a power consumption of 109 mW in normal operation mode.