# FPGA acceleration of GWAS permutation testing

## TL;DR

This paper introduces an FPGA-based tool that dramatically speeds up GWAS permutation testing, making it feasible for large datasets without needing specialized hardware or expertise.

## Contribution

The novel contribution is an FPGA-based cloud-deployable tool for accelerating GWAS permutation testing with significant performance gains.

## Key findings

- The FPGA tool completed 1000 maxT permutations in 22 minutes versus 7 days for PLINK on 40 CPU cores.
- For 100 million adaptive permutations, the FPGA tool required 325 minutes compared to 8.5 days for PLINK.
- The tool handled 700 million adaptive permutations in 33 hours, a task requiring over a month on CPUs.

## Abstract

Summary: Genome-wide association studies (GWASs) analyse genetic variation across many individuals to identify single-nucleotide polymorphisms (SNPs) associated with complex traits. They typically include millions of SNPs from thousands of individuals, creating a multiple testing problem where the probability of false associations increases with the number of SNPs tested. While permutation testing provides accurate control of false positive rates, it is computationally expensive and slow for large datasets. This research presents an FPGA-based tool designed for cloud deployment on AWS EC2 instances that significantly accelerates GWAS permutation testing for continuous phenotypes. The tool implements two algorithms: maxT and adaptive permutation testing. Performance comparisons using a breast cancer dataset (13.7 million SNPs from 3652 individuals) showed large speedups over PLINK running on 40 CPU cores. For 1000 maxT permutations, the FPGA tool completed analysis in 22 min versus PLINK’s 7 days. For 100 million adaptive permutations, FPGA required 325 min compared to PLINK’s 8.5 days. The tool handled 700 million adaptive permutations in 33 h—a workload which would require over a month for CPU-based analysis. FPGA solution provides accessible, order-of-magnitude performance improvements without requiring FPGA expertise or dedicated cluster access.