# Influence of Homoepitaxial Layer Thickness on Flatness and Chemical Mechanical Planarization Induced Scratches of 4H-Silicon Carbide Epi-Wafers

## TL;DR

This paper explores how the thickness of homoepitaxial layers affects the flatness and scratch resistance of 4H-SiC wafers used in high-voltage power devices.

## Contribution

The study reveals how epitaxial thickness influences wafer deformation and scratch propagation under manufacturing conditions.

## Key findings

- Increasing epitaxial thickness beyond 31 μm leads to significant geometric deformation.
- Hydrogen etching and buffer layers reduce scratch propagation from CMP.
- CMP-induced scratches are mitigated during epitaxial growth under HVM conditions.

## Abstract

The integration of thick homoepitaxial layers on silicon carbide (SiC) substrates is critical for enabling high-voltage power devices, yet it remains challenged by substrate surface quality and wafer geometry evolution. This study investigates the relationship between substrate preparation—particularly chemical mechanical planarization (CMP)—and the impact on wafer bow, total thickness variation (TTV), local thickness variation (LTV), and defect propagation during epitaxial growth. Seven 150 mm, 4° off-axis, prime-grade 4H-SiC substrates from a single ingot were processed under high-volume manufacturing (HVM) conditions and grown with epitaxial layers ranging from 12 μm to 100 μm. Metrology revealed a strong correlation between increasing epitaxial thickness and geometric deformation, especially beyond 31 μm. Despite initial surface scratches from CMP, hydrogen etching and buffer layer deposition significantly mitigated scratch propagation, as confirmed through defect mapping and SEM/FIB analysis. These findings provide a deeper understanding of the substrate-to-epitaxy integration process and offer pathways to improve manufacturability and yield in thick-epilayer SiC device fabrication.