# Effect of HZO Thickness Scaling in the Bilayer Ferroelectric Tunnel Junction

**Authors:** Luca Carpentieri, Thomas Mikolajick, Stefan Slesazeck

PMC · DOI: 10.1021/acsaelm.5c00469 · ACS Applied Electronic Materials · 2025-05-26

## TL;DR

This paper explores how changing the thickness of a ferroelectric layer affects the performance of a tunnel junction device.

## Contribution

The study reveals how ferroelectric thickness scaling impacts polarization and tunneling current in bilayer devices.

## Key findings

- Ferroelectric thickness influences remnant polarization and tunneling current in different device states.
- On–Off ratio and memory window depend on thickness and reading voltage conditions.
- Asymmetric stack structure causes imperfect screening and affects data retention in the On state.

## Abstract

This study investigates
the effects of ferroelectric
thickness
scaling in a bilayer-structured ferroelectric tunnel junction. It
was found that both the remnant polarization and the transport mechanisms
exhibit a correlation with the thickness of the ferroelectric film.
While variations in ferroelectric thickness influence the tunneling
current in the Off state, the magnitude of the remnant polarization
significantly affects the current during the On state. Considering
that the On–Off ratio serves as an important figure of merit,
an analysis of the optimal memory window is provided, accounting for
the impact of reading voltage and cycling conditions. Moreover, investigation
of the polarization decay observed at different delay times after
the writing reveals the direct correlation between the depolarization
field and thickness scaling. Retention studies further indicate that
tunneling current decay induced greater vulnerability to the On state,
primarily attributed to the asymmetry of the stack structure, which
results in imperfect screening of polarization charges. Our investigation
into the scaling of ferroelectric thickness emphasizes its critical
importance by examining both ferroelectric properties and device performance.
These findings indicate that the optimization of FTJ for low operation
voltage, long data retention, and high on-current density necessitates
a coordinated optimization of the layer stack structure, establishing
a direct relationship crucial for the future development of hafnia-based
FTJ devices.

## Full text

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## Figures

7 figures with captions in the complete paper: https://tomesphere.com/paper/PMC12160526/full.md

## References

35 references — full list in the complete paper: https://tomesphere.com/paper/PMC12160526/full.md

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Source: https://tomesphere.com/paper/PMC12160526