# Interfacial Chemical and Electrical Performance Study and Thermal Annealing Refinement for AlTiO/4H-SiC MOS Capacitors

## TL;DR

This study improves the performance of SiC-based power devices by refining the AlTiO gate dielectric using ALD and thermal annealing.

## Contribution

The paper demonstrates how ALD and thermal annealing can enhance the electrical and chemical properties of AlTiO gate dielectrics on SiC.

## Key findings

- Annealing improved the leakage current density from ~10−3 to ~10−6 A/cm2 and increased the breakdown field to 7.2 MV/cm.
- XPS analysis showed improved interfacial bonding with Ti atoms in the AlTiO film.
- Thermal annealing increased the bandgap of AlTiO by up to 0.85 eV, leading to better band alignment.

## Abstract

The gate reliability issues in SiC-based devices with a gate dielectric formed through heat oxidation are important factors limiting their application in power devices. Aluminum oxide (Al2O3) and titanium dioxide (TiO2) were combined using the ALD process to form a composite AlTiO gate dielectric on a 4H-SiC substrate. TDMAT and TMA were the precursors selected and deposited at 200 °C, and the samples were Ar or N2 annealed at temperatures ranging from 300 °C to 700 °C. An XPS analysis suggested that the AlTiO film had been deposited with a high overall quality and the involvement of Ti atoms had increased the interfacial bonding with the substrate. The as-deposited MOS structure had band shifts of ΔEC = 1.08 eV and ΔEV = 2.41 eV. After annealing, the AlTiO bandgap increased by 0.85 eV at most, and better band alignment was attained. Leakage current and breakdown voltage characteristic investigations were conducted after Al electrode deposition. The leakage current density and electrical breakdown field of an MOS capacitor structure with a SiC substrate were ~10−3 A/cm2 and 6.3 MV/cm, respectively. After the annealing process, both the measures of the JV performance of the MOS capacitor had improved to ~10−6 A/cm2 and 7.2 MV/cm. The interface charge Neff of the AlTiO layer was 4.019 × 1010 cm−2. The AlTiO/SiC structure fabricated in this work proved the feasibility of adjusting the properties of single-component gate dielectric materials using the ALD method, and using a suitable thermal annealing process has great potential to improve the performance of the compound MOS dielectric layer.