# An area and power efficient ternary serial adder using phase composite ZnO stack channel FETs

## TL;DR

This paper presents a power-efficient ternary serial adder using ZnO-based transistors, offering reduced area and power consumption for low-power applications.

## Contribution

A novel ternary serial adder design using phase composite ZnO stack channel FETs for low power and area efficiency.

## Key findings

- The ternary full adder requires only 12 devices, about 29% of a binary full adder.
- The ternary serial adder achieves a power-delay product of approximately 7 fJ at VDD = 1 V.
- SCFET-based ternary circuits are promising for extremely low-power applications.

## Abstract

Multi-valued logic is the subject of ongoing investigation owing to its potential to reduce the complexity of logic circuits and interconnect lengths, thereby reducing system power consumption. In this work, ternary stack channel field-effect transistors (SCFETs) are used as unit devices to realize multi-valued logic. The thickness of each ZnO layer in the SCFET is modulated to obtain the device parameters to control the intermediate-state range and saturation current. Using the experimental results, ternary circuits are modeled and simulated to demonstrate that the unique characteristics of SCFETs can be utilized in designing a ternary full adder. The designed ternary full adder requires only 12 devices (approximately 29% of the binary full adder device count). The ternary serial adder has a competitive power-delay product value of approximately 7 fJ at VDD = 1 V and an effective oxide thickness of 1 nm. These results indicate that SCFET-based ternary circuits are a promising alternative for extremely low-power applications.

This paper proposes a highly efficient ternary serial adder (TSA) in terms of area and power. The unique characteristics of phase composite ZnO stacked channel field-effect transistors are exploited for the TSA circuit.