# Low-Power and High-Performance Double-Node-Upset-Tolerant Latch Using Input-Splitting C-Element

## TL;DR

This paper introduces a new latch design that improves sensor system reliability by tolerating data errors from double-node upsets while reducing power and delay.

## Contribution

A novel DNUISC latch is proposed, combining input-splitting C-elements with clock gating and fast-path techniques for enhanced robustness and efficiency.

## Key findings

- The DNUISC latch self-recover from single-node upsets and tolerate double-node upsets.
- The design achieves a 55.21% reduction in area-power-delay product compared to existing hardened latches.
- The proposed latch maintains high reliability under varying process, voltage, and temperature conditions.

## Abstract

Data accuracy is critical for sensor systems. As essential components of digital circuits within sensor systems, nanoscale CMOS latches are particularly susceptible to single-node upsets (SNUs) and double-node upsets (DNUs), which can lead to data errors. In this paper, a highly robust Double-Node-Upset-Tolerant Latch-Based on Input Splitting C-Elements (DNUISC) is proposed. The DNUISC latch is designed by interconnecting three sets of input-splitting C-elements to form a feedback loop, and it incorporates clock gating and fast-path techniques to minimize power consumption and delay. Simulations are conducted using the 28 nm process in HSPICE. The simulation results show that the DNUISC can self-recover from any single-node upset and is tolerant of any double-node upset. Compared with existing hardened latches, the DNUISC achieves a 55.21% reduction in area-power-delay product (APDP). Furthermore, the proposed DNUIS demonstrates high reliability and low sensitivity under varying process, voltage, and temperature conditions.