# An Optimized Core Distribution Adaptive Topology Reconfiguration Algorithm for NoC-Based Embedded Systems

## TL;DR

This paper introduces a new algorithm for reconfiguring NoC systems to handle core failures more efficiently and reliably.

## Contribution

A novel adaptive topology reconfiguration algorithm that optimizes core distribution and improves recovery performance.

## Key findings

- The proposed algorithm achieves a 96.70% reconfiguration success rate when faulty cores are below 68.75% of the maximum.
- It outperforms BTTR and BSTR by 14.80% and 9.30% in success rate when 8 cores are faulty in an 8 × 9 REmesh.
- The algorithm reduces recovery time by 98.60% compared to BTTR and by 15.87% compared to BSTR.

## Abstract

In advanced multicore embedded systems, network-on-chip (NoC) is vital for core communication. With a rise in the number of cores, the incidence of core failures rises, potentially affecting system performance and stability. To address the challenges associated with core failures in network-on-chip (NoC) systems, researchers have proposed numerous topology reconfiguration algorithms. However, these algorithms fail to achieve an optimal balance between topology reconfiguration rate and recovery time. Addressing these issues, we propose an adaptive core distribution optimization topology reconfiguration algorithm, which involves the distribution of faulty cores as the main factor for the reconfiguration procedure. This algorithm is based on a 2D REmesh structure to achieve physical topology reconfiguration, optimized through a bidirectional search algorithm, and features an adaptive algorithm for optimizing core distribution. Experimental results show that a 96.70% successful reconfiguration rate with the proposed algorithm can be guaranteed when faulty cores are less than 68.75% of the max faulty cores. In particular, when the faulty cores reach 8 in the 8 × 9 REmesh, the successful reconfiguration rate is 63.60% with the proposed algorithm, which is 14.80% higher than BTTR and 9.30% higher than BSTR. Additionally, the average recovery time of our algorithm is reduced by 98.60% compared with BTTR and by 15.87% compared with BSTR, significantly improving both the performance and reliability in embedded systems.