Analyzing the Impact of Gate Oxide Screening on Interface Trap Density in SiC Power MOSFETs Using a Novel Temperature-Triggered Method
Monikuntala Bhattacharya, Michael Jin, Hengyu Yu, Shiva Houshmand, Jiashu Qian, Marvin H. White, Atsushi Shimbori, Anant K. Agarwal

TL;DR
This paper introduces a new method to analyze defects in silicon carbide MOSFETs and finds that trench devices are more reliable than planar ones, while a screening technique can create new defects.
Contribution
A novel temperature-triggered method (T3VS) is introduced for analyzing interface trap density in SiC MOSFETs.
Findings
Trench gate SiC MOSFETs have significantly lower interface trap density than planar devices.
The SWAP screening method can introduce new defect states near the conduction band edge.
The T3VS method is simpler and more accessible than traditional Dit extraction techniques.
Abstract
This work introduces a novel temperature-triggered threshold voltage shift (T3VS) method to study the energy-dependent Dit distribution close to the conduction band edge in commercial 1.2 kV 4H-SiC MOSFETs with planar and trench gate structures. Traditional Dit extraction methodologies are complicated and require sophisticated instrumentation, complex analysis, and/or prior information related to the device design and fabrication, which is generally unavailable to the consumers of commercial devices. This methodology merely utilizes the transfer characteristics of the device and is straightforward to implement. The Dit analysis using the T3VS method shows that trench devices have significantly lower Dit in comparison to the planar devices, making them more reliable and efficient in practical applications. Furthermore, this study examines the impact of a novel room temperature gate oxide…
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Taxonomy
TopicsSilicon Carbide Semiconductor Technologies · Semiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design
