An Overview of Hot Carrier Degradation on Gate-All-Around Nanosheet Transistors
Huimei Zhou
TL;DR
This paper reviews hot carrier degradation in gate-all-around nanosheet transistors, focusing on reliability challenges in next-generation semiconductor devices.
Contribution
The paper provides a comprehensive review of hot carrier degradation in GAA nanosheet transistors, including geometry and process impacts.
Findings
Hot carrier degradation significantly affects the reliability of gate-all-around nanosheet transistors.
Geometry dependencies and surface orientation have notable impacts on degradation behavior.
Characterization methodologies and self-heating effects are critical for understanding HCD in scaled devices.
Abstract
Gate-All-Around (GAA) Nanosheet (NS) transistors have been identified as the device architecture for 3 nm and beyond as they provide additional scaling benefits. The Hot Carrier (HC) effect cannot be ignored in the development of metal oxide semiconductor field effect transistors (MOSFETs). In this article, we present a comprehensive review of Hot Carrier Degradation (HCD) studies on GAA NS transistors including geometry dependencies, surface orientation impacts, corner effects, characterization methodologies, process impacts and self-heating impacts from different researchers, together with the challenges and outlook, providing an insightful and valuable HCD reliability discussion and review on the cutting-edge technology in continuous MOSFET scaling.
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Taxonomy
TopicsSemiconductor materials and devices · Advancements in Semiconductor Devices and Circuit Design · Ferroelectric and Negative Capacitance Devices