A Review on Micro-Watts All-Digital Frequency Synthesizers
Venkadasamy Navaneethan, Boon Chiat Terence Teo, Annamalai Arasu Muthukumaraswamy, Xian Yang Lim, Liter Siek
TL;DR
This paper reviews low-power all-digital frequency synthesizers for IoT applications, focusing on their design and implementation in CMOS technology.
Contribution
The paper provides a comprehensive review of divider-less low-power frequency synthesizers and architectural advancements in ADPLLs.
Findings
All-digital frequency synthesizers are well-suited for low-power IoT applications due to their CMOS compatibility.
Architectural innovations like DTC-assisted TDC and embedded TDC reduce power consumption in ADPLLs.
Hybrid PLLs and ADFLLs are explored as alternatives for low-power frequency synthesis.
Abstract
This paper reviews recent developments in highly integrated all-digital frequency synthesizers suitable to deploy in low-power internet-of-things (IoT) applications. This review sets low power consumption as a key criterion for exploring the all-digital frequency synthesizer implemented in CMOS fabrication technology. The alignment with mainstream CMOS technology offers high-density, comprehensive, robust signal processing capability, making it very suitable for all-digital phase-locked loops to harvest that capacity, and it becomes inevitable. This review includes various divider-less low-power frequency synthesizers, including all-digital phase-locked loops (ADPLL), all-digital frequency-locked loops (ADFLL), and hybrid PLLs. This paper also discusses the latest architectural developments for ADPLLs to lead to low-power implementation, such as DTC-assisted TDC, embedded TDC, and…
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Taxonomy
TopicsAdvancements in PLL and VCO Technologies · Analog and Mixed-Signal Circuit Design · Electromagnetic Compatibility and Noise Suppression