# An efficient method of modulo adder design for Digital Signal Processing applications

## TL;DR

This paper introduces a more efficient modulo adder design for digital signal processing, reducing area and delay compared to existing methods.

## Contribution

A novel diminished-one modulo adder for 2n+1 with reduced area, delay, and improved ADP and PDP metrics.

## Key findings

- The proposed design reduces area by 23.41% and delay by 31.64% compared to existing designs.
- Synthesis results show 13.71% less area and 14.5% less delay in the new modulo adder.
- The design achieves a 26.2% reduction in ADP and 32.8% improvement in PDP over existing structures.

## Abstract

Modulo adder is a widely used arithmetic component in many Digital Signal Processing (DSP) applications such as Finite Impulse Response (FIR), Infinite Impulse Response (IIR) filters, digital signal processors, image processing modules, discrete cosine transform, and cryptography. Therefore, in this paper, the critical path delay and area of modulo adder are analyzed. An optimized diminished-one modulo adder for 2n+1 is proposed based on the analysis results.•Theoretical comparison shows that the suggested modulo adder involves 23.41 % less area (transistors count) and 31.64 % less delay than the best existing design for an average bit-width.•Synthesis result reveals that the proposed modulo adder involves 13.71 % less area and 14.5 % less delay compared to the best existing modulo adder structure design in the literature for an average bit-width.•To observe the overall efficacy of the suggested modulo adder design, the area delay product (ADP) and power delay product (PDP) values of the proposed and existing modulo adder designs are computed using synthesis data. The values obtained for ADP and PDP reveal that the proposed design achieves a 26.2 % reduction in ADP and a 32.8 % improvement in PDP compared to the best available modulo-adder structure.

Theoretical comparison shows that the suggested modulo adder involves 23.41 % less area (transistors count) and 31.64 % less delay than the best existing design for an average bit-width.

Synthesis result reveals that the proposed modulo adder involves 13.71 % less area and 14.5 % less delay compared to the best existing modulo adder structure design in the literature for an average bit-width.

To observe the overall efficacy of the suggested modulo adder design, the area delay product (ADP) and power delay product (PDP) values of the proposed and existing modulo adder designs are computed using synthesis data. The values obtained for ADP and PDP reveal that the proposed design achieves a 26.2 % reduction in ADP and a 32.8 % improvement in PDP compared to the best available modulo-adder structure.

Image, graphical abstract