# A Complementary Metal-Oxide Semiconductor (CMOS) Analog Optoelectronic Receiver with Digital Slicers for Short-Range Light Detection and Ranging (LiDAR) Systems

**Authors:** Yunji Song, Sung-Min Park

PMC · DOI: 10.3390/mi16020215 · Micromachines · 2025-02-13

## TL;DR

This paper presents a new CMOS analog optoelectronic receiver for LiDAR systems that improves noise rejection and performance with digital slicers.

## Contribution

The paper introduces an ADOR chip with a novel differential architecture and cross-coupled components for enhanced performance in LiDAR applications.

## Key findings

- The ADOR chip achieves a 20 dB dynamic range from 100 μApp to 1 mApp.
- It operates at a 2 Gb/s data rate with 22.7 mW power consumption.
- The design improves common-mode noise rejection and bandwidth using cross-coupled components.

## Abstract

This paper introduces an analog differential optoelectronic receiver (ADOR) integrated with digital slicers for short-range LiDAR systems, consisting of a spatially modulated P+/N-well on-chip avalanche photodiode (APD), a cross-coupled differential transimpedance amplifier (CCD-TIA) with cross-coupled active loads, a continuous-time linear equalizer (CTLE), a limiting amplifier (LA), and dual digital slicers. A key feature is the integration of an additional on-chip dummy APD at the differential input node, which enables the proposed ADOR to outperform a traditional single-ended TIA in terms of common-mode noise rejection ratio. Also, the CCD-TIA utilizes cross-coupled PMOS-NMOS active loads not only to generate the symmetric output waveforms with maximized voltage swings, but also to provide wide bandwidth characteristics. The following CTLE extends the receiver bandwidth further, allowing the dual digital slicers to operate efficiently even at high sampling rates. The LA boosts the output amplitudes to suitable levels for the following slicers. Then, the inverter-based slicers with low power consumption and a small chip area produce digital outputs. The fabricated ADOR chip using a 180 nm CMOS process demonstrates a 20 dB dynamic range from 100 μApp to 1 mApp, 2 Gb/s data rate with a 490 fF APD capacitance, and 22.7 mW power consumption from a 1.8 V supply.

## Full-text entities

- **Diseases:** PD (MESH:D010300), injury to people or property (MESH:C000719191), TIA (MESH:D002546)
- **Chemicals:** LiDAR (-)

## Full text

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## Figures

12 figures with captions in the complete paper: https://tomesphere.com/paper/PMC11857726/full.md

## References

17 references — full list in the complete paper: https://tomesphere.com/paper/PMC11857726/full.md

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Source: https://tomesphere.com/paper/PMC11857726