# Demonstration of Integrated Quasi-Vertical DMOS Compatible with the Bipolar-CMOS-DMOS Process Achieving Ultralow RON,sp

## TL;DR

This paper introduces a new type of MOSFET with a split-gate trench structure that significantly reduces resistance and improves performance beyond traditional silicon limits.

## Contribution

The paper presents a novel SGT-QVDMOS structure that achieves ultralow ON-state resistance using a quasi-vertical design compatible with existing BCD processes.

## Key findings

- The SGT-QVDMOS achieves 11.07 mΩ∙mm2 RON,sp, which is 39.0% lower than the traditional Si limit.
- The device exhibits a threshold voltage of 1.9 V and a breakdown voltage of 48.6 V.
- The quasi-vertical structure enables two-dimensional voltage withstanding and improved forward conducting characteristics.

## Abstract

An integrated quasi-vertical double-diffused MOSFET (DMOS) with split-gate trench (SGT) structure (SGT-QVDMOS), whose specific ON-state resistance (RON,sp) breaks the traditional Si limit significantly, is proposed and fabricated. The measured data of the latest manufactured device is presented. By introducing the vertical gate poly, the split grounded source poly, and the asymmetric thick oxide in the gate trench, the traditional lateral drift region is folded in the SGT-QVDMOS. In this way, the device voltage withstanding mode transforms from one dimension to two dimensions, including the horizontal and the vertical directions. Combining the electric field modulation effect and the reduced lateral area, which benefit from the quasi-vertical structure, the forward conducting characteristic of the SGT-QVDMOS is effectively improved. According to the measured results from the SGT-QVDMOS manufactured by the 180 nm Bipolar-CMOS-DMOS (BCD) process, the ultralow ON-state resistance is obtained. The device achieves 1.9 V VTH, 11.07 mΩ∙mm2 RON,sp, and 48.6 V BV, which is 39.0% lower than the traditional Si limit.