Two CMOS Wilkinson Power Dividers Using High Slow-Wave and Low-Loss Transmission Lines

TL;DR

This paper introduces two compact Wilkinson power dividers using a novel CMOS transmission line structure that performs well at high frequencies.

Contribution

The novelty lies in the use of a multi-layer pseudo coplanar waveguide structure in CMOS for high-performance, small-area power dividers.

Findings

The meandered design achieved 5.1 dB insertion loss and better than 17.5 dB return loss at 60 GHz.

The PCPW structure showed good immunity to layout meanderings, maintaining performance in propagation and impedance.

The core area of the design is very compact at 0.2 mm × 0.23 mm.

Abstract

This work presents two Wilkinson power dividers (WPDs) using multi-layer pseudo coplanar waveguide (PCPW) structures. The PCPW-based WPDs were designed, implemented, and verified in a standard 180 nm CMOS process. The proposed PCPW features high slow-wave and low-loss performances compared to other common transmission lines. The two WPDs are based on the same PCPW structure parameters in terms of line width, spacing, and used metal layers. One WPD was realized in a straight PCPW-based layout, and the other WPD was realized in a meandered PCPW-based layout. Both the two WPDs worked up to V-band frequencies, as expected, which also demonstrates that the PCPW guiding structure is less susceptible to the effects of meanderings on the propagation constant and characteristic impedance. The meandered design shows that the measured insertion losses were about 5.1 dB, and its return losses were better than 17.5 dB at 60 GHz. In addition, its isolation, amplitude imbalance, and phase imbalance were 18.5 dB, 0.03 dB, and 0.4°, respectively. The core area was merely 0.2 mm × 0.23 mm, or 1.8 × 10−3λo2.

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