# A Study on Dual-Gate Dielectric Face Tunnel Field-Effect Transistor for Ternary Inverter

## TL;DR

This paper introduces a new transistor design that enables three output voltage states, improving performance for ternary inverters.

## Contribution

The novel dual-gate dielectric face tunnel FET design enables ternary operation with improved performance indicators.

## Key findings

- The DGDFTFET can produce three stable output voltage levels in a ternary inverter.
- The DGDFTFET outperforms the FTFET in terms of static noise margins and performance indicators.

## Abstract

In this article, we propose a dual-gate dielectric face tunnel field-effect transistor (DGDFTFET) that can exhibit three different output voltage states. Meanwhile, according to the requirements of the ternary operation in the ternary inverter, four related indicators representing the performance of the DGDFTFET are proposed, and we explain the impact of these indicators on the inverter and confirm that better indicators can be obtained by choosing appropriate design parameters for the device. Then, the ternary inverter implemented with this device can exhibit voltage transfer characteristics (VTCs) with three stable output voltage levels and bigger static noise margins (SNMs). In addition, by comparing the indicators of the DGDFTFET and a face tunnel field-effect transistor (FTFET), as well as the SNM of inverters, it is demonstrated that the performance of the DGDFTFET far surpasses the FTFET.