# A Novel IGBT with SIPOS Pillars Achieving Ultralow Power Loss in TCAD Simulation Study

## TL;DR

This paper introduces a new IGBT design using SIPOS pillars that significantly reduces power loss during operation.

## Contribution

The novel SIPOS-IGBT design achieves ultralow power loss by optimizing electric field distribution and carrier injection.

## Key findings

- SIPOS-IGBT shows a uniform electric field distribution in the off state, allowing a thinner drift region.
- The device achieves 58% lower turn-off loss compared to a field-stop IGBT under the same conditions.
- The design improves the balance between conduction and switching losses through enhanced carrier concentration.

## Abstract

A novel insulated gate bipolar transistor with Semi-Insulated POly Silicon (SIPOS) is presented in this paper and analyzed through TCAD simulation. In the off state, the SIPOS-IGBT can obtain a uniform electric field distribution, which enables a thinner drift region under the same breakdown voltage. In the on state, an electron accumulation layer is formed along the SIPOS, which can increase the injection level of the “PiN region” in the device, and the carrier concentration in the drift region is also increased due to the charge balance effect. Moreover, the SIPOS-IGBT can achieve a quick and thorough depletion in the drift region during the turn-off transient, which can greatly reduce the turn-off loss of the SIPOS-IGBT. These advantages improve the tradeoff between the conduction and switching losses. According to the simulation results, the SIPOS-IGBT obtained a 58% lower turn loss than that of a field-stop (FS) IGBT and 30% lower than an HK-IGBT with the same on-state voltage.