Design and Analysis of Digitally Tunable Transconductance Amplifier (DTTA) Using CNTFETs

TL;DR

This paper presents a digitally tunable amplifier design using carbon nanotube transistors, enabling flexible performance adjustments without hardware changes.

Contribution

The novelty lies in using CNTFETs to create a digitally tunable transconductance amplifier with no hardware modifications.

Findings

CNTFET-based DTTA design allows transconductance tuning without hardware changes.

The design was verified using a 32 nm CNTFET model and HSPICE simulations.

CNTFET modeling techniques were detailed for realistic circuit simulations.

Abstract

Carbon nanotube-FETs (CNTFETs) have become a potential challenger because of their exceptional electrical properties and compatibility with conventional CMOS technology. The design and study of digitally tunable transconductance amplifiers (DTTAs) using CNTFETs are the main topics of this work. By utilizing the special characteristics of CNTFETs, the suggested DTTA design makes transconductance tunable, providing a versatile method of adjusting amplifier settings without requiring modifications to the hardware architecture. This study provides a complete description of the CNTFET modeling techniques utilized for realistic circuit simulations, along with a detailed analysis of the DTTA based on CNTFETs. The circuit is implemented using a 32 nm CNTFET model and verified results with HSPICE.

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Full text

1. Introduction

As semiconductor technology advances, CNTFET-based circuits show the potential to overcome the limits of classical CMOS in developing applications such as high-frequency communication systems, sensor interfaces, and medicinal devices. However, real deployment may need to address concerns about manufacturing scalability, cost-effectiveness, and long-term stability related to CNTFET manufacture and integration [1–3].

Filters having a very low cut-off frequency are required for the processing of physiological signals. The frequency range of commonly utilized physiological signals ranges from sub-Hz to a few KHz. The operational transconductance amplifier (OTA) is a key component in low-frequency analog signal processing. These applications need the development of OTA with extremely low transconductance (gm) [4, 5]. Transconductance amplifiers transform voltage signals into current signals in analog and mixed-signal electronics. The entire efficacy of different applications such as signal processing, communication systems, and sensor interfaces is determined by their performance [6, 7]. The ability to tune amplifier characteristics is crucial in adapting these circuits to varied settings without sacrificing efficiency [8–10].

Transconductance amplifiers based on silicon have intrinsic restrictions, notably in terms of power requirement, operating frequency, and flexibility. As an alternative, integrating CNTFETs provides a convincing solution to these restrictions. CNTFETs' outstanding electron mobility, resilience, and nanoscale dimensions enable circuit designers to push the performance envelope [11, 12].

In this work, we find the feature of carbon nanotube (CNT) for increasing the drain current. This feature is utilized for the digitally tunable transconductance amplifier. Thus, drain current can be controlled by the number of CNTs for a digital control stage. Here, we have discussed the control of drain current depends on the diameter and number of CNTs in a carbon nanotube-FET.

First, in CMOS, the minimum W/L ratio of PMOS to NMOS is 2.5 times. In order to have smooth performance, the W/L ratio of PMOS is usually kept higher than 2.5. NMOS has electrons as majority-charge carriers, and PMOS has holes as majority-charge carriers. Electrons have mobility 2.7 times higher than holes. The main reason behind making PMOS larger is that the rise time and fall time of the gate should be equal and for the resistance of the NMOS and PMOS should be the same. This can be achieved only by sizing the PMOS 3 times to the NMOS sizing. However, in the case of CNFET, pCNFET and nCNFET can have the same width because the mobility in the pCNFET and nCNFET is the same.

This study aims to investigate the design and analysis of digitally tunable transconductance amplifiers (DTTAs) that take advantage of the capabilities of CNTFETs. The major goal is to use CNTFET intrinsic features to improve circuit performance including gain, power efficiency, bandwidth, and linearity [13, 14]. The amplifier's properties may be dynamically modified to accommodate different operating needs by including digital tuning mechanisms, significantly broadening the area of its use [15–18]. A carbon nanotube field effect transistor (CNTFET) has a cross-sectional view as shown in Figure 1.

The paper is structured in the following way. The design aspect of the digitally tunable transconductance amplifier (DTTA) is presented in Section 2. Section 3 illustrates the simulation results of the presented DTTA while Section 4 concludes the paper.

2. Proposed Digitally Tunable Transconductance Amplifier (DTTA)

Two input voltages are used by the operational transconductance amplifier (OTA), which generates an output current proportional to the difference between the two voltages. The output current of OTA is expressed by (1), where gm is the transconductance of the amplifier, and the biasing current governs its value (IBias) applied to the circuit [19–21].

$$[eqn]$$

Further, the design parameters of CNTFET are given in Table 1.

The design aspect and parameters are kept in consideration for the CNFETs. The CNFETs have wide flexibility in terms of the width of the CNFET-based transistor (W), number of CNTs in the channel (N), and inter-CNT spacing (S).

In this work, CNTs are utilized which have very high drive currents, less scattering, and near ballistic transport of charge carriers. The feature of the carbon nanotube is explored by which the drain current in a transistor is controlled by CNTs in the channel. This property can be utilized to design a DTTA. It enhances the operability and flexibility of the transconductance amplifier. The proposed method uses multiple CNTs to increase the drain current of the transistor.

The proposed circuit is novel as the following design parameters of CNFET are considered: the CNT's diameter (DCNT), the width of the CNFET-based transistor (W), the number of CNTs in the channel (N), and the inter-CNT spacing (S). The width of CNFETs depends on the number of CNTs used in each stage and is calculated by the following equation:

$$[eqn]$$

where DCNT is the diameter of CNT, S is interspacing between CNTs, and N is the number of CNTs in CNFET. In the given circuit, the transistor stages (M1 − M14) and (M27 − M30) have four CNTs. Further, to double the current in the next stage (M15 − M18) and (M31 − M34), the number of CNTs should be doubled, i.e., eight. Similarly, stages (M19 − M22) and (M35 − M38) contain sixteen CNTs.

The digitally tunable approach is now being used for the transconductance amplifier. Many digitally adjustable approaches have been described in the literature [22–25]. The digital control approach also increases the circuit's reconfigurability. A digitally controlled voltage gain amplifier (VGA) with a CMOS digitally programmable current conveyor was presented in 2008 [22]. A current-controlled conveyor (CCC-II) with digital control via a current division network (CDN) has also been proposed to achieve a multiphase oscillator [23]. A simplified block diagram of the proposed DTTA is shown in Figure 2. The voltage is applied through terminal Y1 and Y2, and the output is taken from I0 terminal. Additionally, “n” represents the control word (a2; a1; a0) which is used to tune the transconductance.

Furthermore, the authors [24] describe a CMOS-based digitally programmable current conveyor-II that employs four bits to regulate the Z+ terminal's current. Next, to realize the digitally programmable current follower (DP-CF), the current division cell (CDC) is used in the approaches as described in [25].

While, in carbon nanotube-FETs, the drain current increases by increasing the number or diameter of CNTs, in MOSFETs, the drain current (ID) is enhanced by raising the transistor width [15, 24]. This implies that by doubling the number of tubes in a carbon nanotube-FET, we can double the current.

2.1. Circuit Description

Figure 3 illustrates the suggested digitally tunable transconductance amplifier (DTTA). Transistors M1 and M2 and M3 and M4 constitute two differential amplifiers driven by transistors M5 and M6, which function as a current mirror. Furthermore, transistors M7 and M10 provide the necessary feedback action to ensure that the voltage VX is independent of the current pulled from terminal X. Additionally, the total of M1 and M4 drain currents equals M2 and M3 drain currents. Moreover, the drain currents of transistors M8 and M9 would be equivalent as they are biased with comparable gate voltages (and their source voltages are also equal). This would get the following for matching M8 and M9:

$$[eqn]$$

The current at terminal X(IX) is transferred as n∗IX to the Z1 terminal through transistors M7, M10 − M22. The current is delivered −n∗IX to the Z2 terminal by employing an additional current mirror stage (M23 − M38).

The voltages VZ1 and VZ2 develop at node Z1 and Z2, which are further applied to gates of M44 and M45 transistors. The transistors M39 − M46 form a structure to generate the output current (I0) which is proportional to the differential inputs, VZ1 and VZ2.

In the given circuit, transistor stages (M1 − M14) and (M27 − M30) have four CNTs. Further, to double the current in the next stage (M15 − M18) and (M31 − M34), number of CNTs should be doubled, i.e., eight. Similarly, stages (M19 − M22) and (M35 − M38) contain sixteen CNTs. The equation for the current can be represented as follows:

$$[eqn]$$

Here, “n” represents the digitally tunable word. For a 3 bit digital tunable word, its value ranges from 0 to 7. Table 2 illustrates the dependency of current gain on the digital tunable word (n). Further, in the next stage, transistors (M39 − M42) have four CNTs and transistors (M43 − M46) have one CNT. For the suggested DTTA, the supply voltage and bias voltage (VBB) have been maintained at 0.7 V and −0.36V, respectively. The detailed dimensions of CNFETs are given in Table 3.

For the currents IX and IZ, the circuit analysis of Figure 3 yields the relations (6) and (7). It is also possible to acquire the voltages of the Z1 and Z2 nodes using (8). The expression for VZ1 and VZ2 may be expressed as (9) after applying the values of IZ1 and IZ2.

$$[eqn]$$ $$[eqn]$$ $$[eqn]$$ $$[eqn]$$ $$[eqn]$$

Considering the characteristics of the OTA, the output current expression may be expressed as follows: (10). If R1=R2=R, R3=2R and putting the value of VZ1 and VZ2, we find (11) and (12).

$$[eqn]$$ $$[eqn]$$ $$[eqn]$$

By comparing equations (1) and (12), it is seen that gm is controlled by the tunable word “n”.

The output current and transconductance are also related. Equations (11) and (12) give the relation between the output current and transconductance.

3. Simulation Results

Additionally, Figure 4 depicts the linear range of the digitally tunable transconductance amplifier (DTTA) of Figure 3. Here, the resistors R1=R2=1K and R3=2K take the value of the digitally tunable word (n) as one. Transconductance has a linear range of 94 mV and a simulated value of 24 pA/V. DTTA has two maximum and lowest values, 24 pA/V and 140 pA/V, respectively. The DTTA's linear range varies from 22 mV to 94 mV. The fluctuation in the DTTA's linear range with the digitally adjustable word is shown in Figure 5.

With a change in the tunable word (n), Table 4 displays the linear ranges and simulated transconductance values of the digitally tunable transconductance amplifier (DTTA). This indicates that there is flexibility in selecting alternative transconductance values using the proposed circuit.

The digital inputs are applied through the digital word (a2; a1; a0) which are the gates of transistors. The current at terminal X(IX) is transferred as n∗IX to the Z1 terminal through transistors M7, M10 − M22. The current is delivered −n∗IX to the Z2 terminal by employing an additional current mirror stage (M23 − M38). The voltages VZ1 and VZ2 develop at nodes Z1 and Z2, which are further applied to the gates of M44 and M45 transistors. The transistors M39 − M46 form a structure to generate the output current (I0) which is proportional to the differential inputs, VZ1 and VZ2 as discussed in Section 2.1.

4. Conclusion

This study contributes to the integration of sophisticated nanoscale devices into analog circuit design by providing a digitally tunable transconductance amplifier (DTTA) based on CNTFETs. The circuit uses 0.7V of power supply. The range of transconductance achieved by the proposed DTTA is 24 pA/V-140 pA/V through the tunable word (000–111) with a linear range of 22 mV–94 mV. The reported results highlight the potential of this technique to change circuit design approaches, providing new levels of flexibility and performance for future electronic systems. These design approaches may help the progress of current electronic systems by improving circuit performance and providing flexibility, opening the way for more efficient and adaptable integrated circuits in the future. Continued research and development in this area will be critical in achieving the full potential of low-power CNTFET-based circuits for a variety of applications.